PDF AD9862 Data sheet ( Hoja de datos )

Número de pieza	AD9862
Descripción	Mixed-Signal Front-End (MxFE) Processor for Broadband Communications
Fabricantes	Analog Devices
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No Preview Available ! a Mixed-Signal Front-End (MxFE™) Processor for Broadband Communications AD9860/AD9862* FEATURES Mixed-Signal Front-End Processor with Dual Converter Receive and Dual Converter Transmit Signal Paths Receive Signal Path Includes: Two 10-/12-Bit, 64 MSPS Sampling A/D Converters with Internal or External Independent References, Input Buffers, Programmable Gain Amplifiers, Low-Pass Decimation Filters, and a Digital Hilbert Filter Transmit Signal Path Includes: Two 12-/14-Bit, 128 MSPS D/A Converters with Programmable Full-Scale Output Current, Channel Independent Fine Gain and Offset Control, Digital Hilbert and Interpolation Filters, and Digitally Tunable Real or Complex Up-Converters Delay-Locked Loop Clock Multiplier and Integrated Timing Generation Circuitry Allow for Single Crystal or Clock Operation Programmable Output Clocks, Serial Programmable Interface, Programmable Sigma-Delta, Three Auxiliary DAC Outputs and Two Auxiliary ADCs with Dual Multiplexed Inputs APPLICATIONS Broadband Wireless Systems Fixed Wireless, WLAN, MMDS, LMDS Broadband Wireline Systems Cable Modems, VDSL, PowerPlug Digital Communications Set-Top Boxes, Data Modems GENERAL DESCRIPTION The AD9860 and AD9862 (AD9860/AD9862) are versatile integrated mixed-signal front-ends (MxFE) that are optimized for broadband communication markets. The AD9860/AD9862 are cost effective, mixed signal solutions for wireless or wireline standards based or proprietary broadband modem systems where dynamic performance, power dissipation, cost, and size are all critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs; the AD9862 has 12-bit ADCs and 14-bit DACs. The AD9860/AD9862 receive path (Rx) consists of two channels that each include a high performance, 10-/12-bit, 64 MSPS analog- to-digital converter (ADC), input buffer, Programmable Gain Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The Rx can be used to receive real, diversity, or I/Q data at baseband or low IF. The input buffers provide a constant input impedance for both channels to ease impedance matching with external com- ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain Protected by U.S.Patent No. 5,969,657; other patents pending. MxFE is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM VIN+A VIN–A VIN+B VIN–B SIGDELT AUX_DAC_A AUX_DAC_B AUX_DAC_C AUX_ADC_A1 AUX_ADC_A2 AUX_ADC_B1 AUX_ADC_B2 IOUT+A IOUT–A IOUT+B IOUT–B 1x PGA ADC BYPASSABLE LOW-PASS HILBERT DECIMATION FILTER FILTER 1x PGA ADC LOGIC LOW ⌺-⌬ AD9860/AD9862 AUX DAC SPI REGISTERS AUX DAC AUX DAC AUX ADC Rx PATH TIMING Tx PATH TIMING CLOCK DISTRIBUTION BLOCK DLL 1؋, 2؋, 4؋ PGA PGA AUX ADC BYPASSABLE DIGITAL QUADRATURE MIXER BYPASSABLE DIGITAL QUADRATURE MIXER DAC DAC FS/4 FS/8 BYPASSABLE LOW-PASS INTERPOLATION FILTER NCO HILBERT FILTER RxA DATA [0:11] RxB DATA [0:11] SPI INTERFACE OSC1 OSC2 CLKOUT1 CLKOUT2 Tx DATA [0:13] range for both channels. The output data bus can be multi- plexed to accommodate a variety of interface types. The AD9860/AD9862 transmit path (Tx) consists of two chan- nels that contain high performance, 12-/14-bit, 128 MSPS digital-to-analog converters (DAC), programmable gain amplifiers (TxPGA), interpolation filters, a Hilbert filter, and digital mixers for complex or real signal frequency modulation. The Tx latch and demultiplexer circuitry can process real or I/Q data. Interpo- lation rates of 2ϫ and 4ϫ are available to ease requirements on an external reconstruction filter. For single channel systems, the digital Hilbert filter can be used with an external quadrature modulator to create an image rejection architecture. The two 12-/14-bit, high performance DACs produce an output signal that can be scaled over a 20 dB range by the TxPGA. A programmable delay-locked loop (DLL) clock multiplier and integrated timing circuits enable the use of a single external reference clock or an external crystal to generate clocking for all internal blocks and also provides two external clock outputs. Additional features include a programmable sigma-delta output, four auxiliary ADC inputs and three auxiliary DAC outputs. Device programmability is facilitated by a serial port interface (SPI) combined with a register bank. The AD9860/AD9862 is available in a space saving 128-lead LQFP. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 1 page ABSOLUTE MAXIMUM RATINGS1 Power Supply (VAS, VDS) . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Digital Inputs . . . . . . . . . . . . . . . . –0.3 V to DRVDD + 0.3 V Analog Inputs . . . . . . . . . . . . . . –0.3 V to AVDD (IQ) + 0.3 V Operating Temperature2 . . . . . . . . . . . . . . . . . –40؇C to +70؇C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150؇C Storage Temperature . . . . . . . . . . . . . . . . . . . –65؇C to +150؇C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300؇C NOTES 1Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. 2The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40؇C to +85؇C) when operated in Half Duplex Mode. AD9860/AD9862 EXPLANATION OF TEST LEVELS I. Devices are 100% production tested at 25ºC and guaranteed by design and characterization testing for the extended industrial temperature range (–40ºC to +70ºC). II. Parameter is guaranteed by design and/or characterization testing. III. Parameter is a typical value only. NA. Test level definition is not applicable. THERMAL CHARACTERISTICS Thermal Resistance 128-Lead LQFP ␪JA = 29ºC/W Model Temperature Range ORDERING GUIDE Package Description Package Option AD9860BST AD9862BST AD9860PCB AD9862PCB –40∞C to +70∞C –40∞C to +70∞C* 128-Lead Low Profile Plastic Quad Flatpack (LQFP) 128-Lead Low Profile Plastic Quad Flatpack (LQFP) Evaluation Board with AD9860 Evaluation Board with AD9862 ST-128B ST-128B *The AD9860/AD9862 have been characterized to operate over the industrial temperature range (–40 ؇C to +85؇C) when operated in Half Duplex Mode. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9860/AD9862 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –5– 5 Page –50 –55 BUFFERED BYPASS 2V INPUT, 1؋ GAIN –60 BUFFERED 2V –65 INPUT, 1؋ GAIN –70 –75 –80 BUFFERED 1V –85 INPUT, 2؋ GAIN BUFFERED BYPASS –90 1V INPUT, 2؋ GAIN –95 –100 0 10 100 INPUT FREQUENCY – MHz 1000 TPC 19. Rx THD vs. fIN, FADC = 64 MSPS –50 –55 –60 –65 BUFFERED BYPASS –70 1V INPUT, 2؋ GAIN –75 BUFFERED BYPASS 2V INPUT, 1؋ GAIN –80 –85 –90 BUFFERED 1V –95 BUFFERED 2V INPUT, 2؋ GAIN INPUT, 1؋ GAIN –100 0 10 100 1000 INPUT FREQUENCY – MHz TPC 22. Rx SFDR @ 64 MSPS 1 0 –1 –2 –3 –4 –5 –6 1 NO BUFF 2V ؋1 BUFF 1V ؋2 BUFF 2V ؋1 10 100 INPUT FREQUENCY – MHz 1000 TPC 25. Rx Input Attenuation –50 AD9860 LOW POWER MODE 1, BUFFER –55 ENABLED, 1V p-p INPUT, –60 2؋ RxPGA GAIN AD9862 LOW POWER MODE 1, BUFFER ENABLED, 1V p-p INPUT, 2؋ RxPGA GAIN –65 –70 –75 –80 –85 –90 0 AD9860 LOW POWER MODE 1, BUFFER BYPASSED, 2V p-p INPUT, 1؋ RxPGA GAIN AD9862 LOW POWER MODE 1, BUFFER BYPASSED, 2V p-p INPUT, 1؋ RxPGA GAIN 50 100 150 200 250 300 fIN – MHz TPC 20. Rx THD vs. fIN, FADC = 32 MSPS –50 AD9862 LOW POWER MODE 1, –55 BUFFER ENABLED, 1V p-p INPUT, 2؋ RxPGA GAIN AD9860 LOW POWER MODE 1, –60 AD9860 BUFFER BYPASSED, LOW POWER MODE 1, 2V p-p INPUT, –65 BUFFER ENABLED, 1؋ RxPGA GAIN 1V p-p INPUT, –70 2؋ RxPGA GAIN –75 –80 –85 –90 –95 0 AD9862 LOW POWER MODE 1, BUFFER BYPASSED, 2V p-p INPUT, 1؋ RxPGA GAIN 50 100 150 200 250 fIN – MHz 300 TPC 23. Rx SFDR @ 32 MSPS 280 270 260 250 240 230 220 210 200 190 180 0 20 40 60 fIN – MHz 80 TPC 26. Rx Input Buffer Impedance vs. fIN 100 AD9860/AD9862 –50 AD9860 LOW POWER MODE 2, BUFFER –55 ENABLED, 1V p-p INPUT, –60 2؋ RxPGA GAIN –65 AD9862 LOW POWER MODE 2, BUFFER ENABLED, 1V p-p INPUT, 2؋ RxPGA GAIN –70 –75 –80 –85 –90 0 AD9860 LOW POWER MODE 2, BUFFER BYPASSED, 2Vp-p INPUT, 1؋ RxPGA GAIN AD9862 LOW POWER MODE 2, BUFFER BYPASSED, 2V p-p INPUT, 1؋ RxPGA GAIN 50 100 150 200 250 300 fIN – MHz TPC 21. Rx THD vs. fIN, FADC = 16 MSPS –50 AD9860 LOW POWER MODE 2, –55 BUFFER BYPASSED, 1V p-p INPUT, 2؋ RxPGA GAIN –60 AD9860 LOW POWER MODE 2, –65 BUFFER ENABLED, 1V p-p INPUT, –70 2؋ RxPGA GAIN –75 –80 –85 –90 –95 0 AD9862 LOW POWER MODE 2, BUFFER BYPASSED, 2V p-p INPUT, 1؋ RxPGA GAIN AD9862 LOW POWER MODE 2, BUFFER ENABLED, 1V p-p INPUT, 2؋ RxPGA GAIN 50 100 150 200 250 fIN – MHz 300 TPC 24. Rx SFDR @ 16 MSPS 800 700 NOMINAL 600 500 32MSPS LP MODE 400 300 16MSPS LP MODE 200 100 0 0 10 20 30 40 50 60 70 fADC – MSPS TPC 27. Rx Analog Power Consumption REV. 0 –11– 11 Page

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