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AD9860 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9860
Beschreibung Mixed-Signal Front-End (MxFE) Processor for Broadband Communications
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9860 Datasheet, Funktion
a Mixed-Signal Front-End (MxFE) Processor
for Broadband Communications
AD9860/AD9862*
FEATURES
Mixed-Signal Front-End Processor with Dual Converter
Receive and Dual Converter Transmit Signal Paths
Receive Signal Path Includes:
Two 10-/12-Bit, 64 MSPS Sampling A/D Converters
with Internal or External Independent References,
Input Buffers, Programmable Gain Amplifiers,
Low-Pass Decimation Filters, and a Digital Hilbert Filter
Transmit Signal Path Includes:
Two 12-/14-Bit, 128 MSPS D/A Converters with
Programmable Full-Scale Output Current, Channel
Independent Fine Gain and Offset Control, Digital
Hilbert and Interpolation Filters, and Digitally Tunable
Real or Complex Up-Converters
Delay-Locked Loop Clock Multiplier and Integrated
Timing Generation Circuitry Allow for Single Crystal
or Clock Operation
Programmable Output Clocks, Serial Programmable
Interface, Programmable Sigma-Delta, Three Auxiliary
DAC Outputs and Two Auxiliary ADCs with Dual
Multiplexed Inputs
APPLICATIONS
Broadband Wireless Systems
Fixed Wireless, WLAN, MMDS, LMDS
Broadband Wireline Systems
Cable Modems, VDSL, PowerPlug
Digital Communications
Set-Top Boxes, Data Modems
GENERAL DESCRIPTION
The AD9860 and AD9862 (AD9860/AD9862) are versatile
integrated mixed-signal front-ends (MxFE) that are optimized
for broadband communication markets. The AD9860/AD9862
are cost effective, mixed signal solutions for wireless or wireline
standards based or proprietary broadband modem systems where
dynamic performance, power dissipation, cost, and size are all
critical attributes. The AD9860 has 10-bit ADCs and 12-bit DACs;
the AD9862 has 12-bit ADCs and 14-bit DACs.
The AD9860/AD9862 receive path (Rx) consists of two channels
that each include a high performance, 10-/12-bit, 64 MSPS analog-
to-digital converter (ADC), input buffer, Programmable Gain
Amplifier (RxPGA), digital Hilbert filter, and decimation filter. The
Rx can be used to receive real, diversity, or I/Q data at baseband or
low IF. The input buffers provide a constant input impedance for
both channels to ease impedance matching with external com-
ponents (e.g., SAW filter). The RxPGA provides a 20 dB gain
*Protected by U.S.Patent No. 5,969,657; other patents pending.
MxFE is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VIN+B
VIN–B
SIGDELT
AUX_DAC_A
AUX_DAC_B
AUX_DAC_C
AUX_ADC_A1
AUX_ADC_A2
AUX_ADC_B1
AUX_ADC_B2
IOUT+A
IOUT–A
IOUT+B
IOUT–B
1x PGA
ADC
BYPASSABLE LOW-PASS HILBERT
DECIMATION FILTER
FILTER
1x PGA
ADC
LOGIC LOW
-
AD9860/AD9862
AUX DAC
SPI REGISTERS
AUX DAC
AUX DAC
AUX ADC
Rx PATH
TIMING
Tx PATH
TIMING
CLOCK
DISTRIBUTION
BLOCK
DLL
1؋, 2؋, 4؋
PGA
PGA
AUX ADC
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
BYPASSABLE
DIGITAL
QUADRATURE
MIXER
DAC
DAC
FS/4
FS/8
BYPASSABLE
LOW-PASS
INTERPOLATION
FILTER
NCO
HILBERT
FILTER
RxA DATA
[0:11]
RxB DATA
[0:11]
SPI
INTERFACE
OSC1
OSC2
CLKOUT1
CLKOUT2
Tx DATA
[0:13]
range for both channels. The output data bus can be multi-
plexed to accommodate a variety of interface types.
The AD9860/AD9862 transmit path (Tx) consists of two chan-
nels that contain high performance, 12-/14-bit, 128 MSPS
digital-to-analog converters (DAC), programmable gain amplifiers
(TxPGA), interpolation filters, a Hilbert filter, and digital mixers
for complex or real signal frequency modulation. The Tx latch
and demultiplexer circuitry can process real or I/Q data. Interpo-
lation rates of 2ϫ and 4ϫ are available to ease requirements on
an external reconstruction filter. For single channel systems, the
digital Hilbert filter can be used with an external quadrature
modulator to create an image rejection architecture. The two
12-/14-bit, high performance DACs produce an output signal
that can be scaled over a 20 dB range by the TxPGA.
A programmable delay-locked loop (DLL) clock multiplier and
integrated timing circuits enable the use of a single external
reference clock or an external crystal to generate clocking for all
internal blocks and also provides two external clock outputs.
Additional features include a programmable sigma-delta output,
four auxiliary ADC inputs and three auxiliary DAC outputs.
Device programmability is facilitated by a serial port interface
(SPI) combined with a register bank. The AD9860/AD9862 is
available in a space saving 128-lead LQFP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






AD9860 Datasheet, Funktion
AD9860/AD9862
PIN CONFIGURATION
AUX_ADC_A1 1
AGND 2
AVDD 3
AVDD 4
SIGDELT 5
AUX_DAC_A 6
AUX_DAC_B 7
AUX_DAC_C 8
AGND 9
DLL_Lock 10
AGND 11
NC 12
AVDD 13
OSC1 14
OSC2 15
AGND 16
CLKSEL 17
AVDD 18
AGND 19
AVDD 20
REFIO 21
FSADJ 22
AVDD 23
AGND 24
IOUT–A 25
IOUT+A 26
AGND 27
AGND 28
IOUT+B 29
IOUT–B 30
AGND 31
AVDD 32
DVDD 33
DGND 34
DGND 35
DVDD 36
Tx11/13 (MSB) 37
Tx10/12 38
PIN 1
IDENTIFIER
AD9860/AD9862
TOP VIEW
(Not to Scale)
NC = NO CONNECT
102 REFB_B
101 REFT_B
100 AGND
99 AVDD
98 AVDD
97 AUX_SPI_csb
96 AUX_SPI_clk
95 AUX_SPI_do
94 DGND
93 DVDD
92 RxSYNC
91 D9/D11B (MSB)
90 D8/D10B
89 D7/D9B
88 D6/D8B
87 D5/D7B
86 D4/D6B
85 D3/D5B
84 D2/D4B
83 D1/D3B
82 D0/D2B
81 NC/D1B
80 NC/D0B
79 D9/D11A (MSB)
78 D8/D10A
77 D7/D9A
76 D6/D8A
75 D5/D7A
74 D4/D6A
73 D3/D5A
72 D2/D4A
71 D1/D3A
70 D0/D2A
69 NC/D1A
68 NC/D0A
67 DGND
66 DVDD
65 CLKOUT1
–6– REV. 0

6 Page









AD9860 pdf, datenblatt
AD9860/AD9862
Register Name Address2
General
Rx Power Down
Rx A
Rx B
Rx Misc
Rx I/F
0
1
2
3
4
5
Rx Digital
RSV
Tx Power Down
6
7
8
RSV
Tx A Offset
9
10
Tx A Offset
Tx B Offset
11
12
Tx B Offset
Tx A Gain
Tx B Gain
Tx PGA Gain
Tx Misc
Tx I/F
13
14
15
16
17
18
Tx Digital
Tx Modulator
NCO Tuning
Word
NCO Tuning
Word
NCO Tuning
Word
DLL
19
20
21
22
23
24
CLKOUT
25
Aux ADC A2 26
Aux ADC A2 27
Aux ADC A1 28
Aux ADC A1 29
Aux ADC B2 30
Aux ADC B2 31
Aux ADC B1 32
Aux ADC B1 33
Aux ADC Control 34
Aux ADC Clock 35
Aux DAC A
36
Aux DAC B
37
Aux DAC C 38
Aux DAC
39
Update Aux DAC 40
DAC Control 41
REGISTER MAP (0x00–0x3F)1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Purpose
SDIO BiDir
VREF (diff)
Byp Buffer A
Byp Buffer B
LSB First
VREF
DAC A Offset [1:0]
DAC B Offset [1:0]
DAC A Coarse Gain
DAC B Coarse Gain
Tx Retime
Soft Reset
Rx Digital Rx Channel B Rx Channel A Buffer B
Buffer A
All Rx
RxPGA A
RxPGA B
HS Duty Cycle Shared Ref Clk Duty
Three State
Rx Retime Twos
Inv RxSync Mux Out
Complement
2 Channel Keep ve Hilbert
Decimate
Reserved for Future Use
Alt Timing TxOff Enable Tx Digital
Mode
Tx Analog Power Down [2:0]
Reserved for Future Use
DAC A Offset
Direction
DAC A Offset [9:2]
DAC B Offset
Direction
DAC B Offset [9:2]
DAC A Fine Gain
DAC B Fine Gain
Tx PGA Gain
Slave Enable Tx PGA Fast
Q/I Order
Inv TxSync
Twos
Inverse
Complement Sample
2 Edges
Interleaved
2 Data Paths Keep ve Hilbert
Interpolation Control
Neg. Fine Tune Fine Mode Real Mix Neg. Coarse Tune Coarse Modulation
SPI Setup
Receive
Path
Setup
Transmit
Path
Setup
FTW [7:0]
FTW [15:8]
FTW [23:16]
Reserved
Input Control ADC Div 2
Clock
DLL Multiplier
CLKOUT2 Divide Factor Inv2
Dis2
Aux ADC A2 Data [1:0]
Aux ADC A2 Data [9:2]
Aux ADC A1 Data [1:0]
Aux ADC A1 Data [9:2]
Aux ADC B2 Data [1:0]
Aux ADC B2 Data [9:2]
Aux ADC B1 Data [1:0]
Aux ADC B1 Data [9:2]
Aux SPI
SelBnot A Refsel B
Select B
Start B
Slave Enable
Aux DAC A
Aux DAC B
Aux DAC C
Inv C
DLL
Power Down
Inv1
DLL
FAST
Dis1
NCO
Setup
Clock
Setup
Auxiliary
ADC Data
and Setup
Refsel A
Select A
Start A
CLK/4
Update C
Update B
Update A
Auxiliary
DAC Data
and Setup
Power Down C Power Down B Power Down A
Inv B
Inv A
SigDelt
SigDelt
42
43
Sigma-Delta Control Word [3:0]
Sigma-Delta Control Word [11:4]
Flag Sigma-
Delta Data
and Setup
ADC Low Power 49, 50
Low Power Register for Rx Path Operation below 32 MSPS
RSV 4462
Reserved for Future Use
63 Chip Rev ID
NOTES
1 When writing to a register with unassigned register bit(s), a logic low must be written to the unassigned bit(s). By default, after power up or RESET, all registers
are set low, except for the bits in the shaded boxes, which are set high.
2 Decimal
Rx Low
Power
Reserved
Chip ID
–12–
REV. 0

12 Page





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