Datenblatt-pdf.com


AD9854 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9854
Beschreibung CMOS 300 MHz Quadrature Complete-DDS
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
AD9854 Datasheet, Funktion
CMOS 300 MSPS Quadrature
Complete DDS
AD9854
FEATURES
300 MHz internal clock rate
FSK, BPSK, PSK, chirp, AM operation
Dual integrated 12-bit digital-to-analog converters (DACs)
Ultrahigh speed comparator, 3 ps rms jitter
Excellent dynamic performance
80 dB SFDR at 100 MHz (±1 MHz) AOUT
4× to 20× programmable reference clock multiplier
Dual 48-bit programmable frequency registers
Dual 14-bit programmable phase offset registers
12-bit programmable amplitude modulation and
on/off output shaped keying function
Single-pin FSK and BPSK data interfaces
PSK capability via input/output interface
Linear or nonlinear FM chirp functions with single-pin
frequency hold function
Frequency-ramped FSK
<25 ps rms total jitter in clock generator mode
Automatic bidirectional frequency sweeping
Sin(x)/x correction
Simplified control interfaces
10 MHz serial 2- or 3-wire SPI compatible
100 MHz parallel 8-bit programming
3.3 V single supply
Multiple power-down functions
Single-ended or differential input reference clock
Small, 80-lead LQFP or TQFP with exposed pad
APPLICATIONS
Agile, quadrature LO frequency synthesis
Programmable clock generators
FM chirp source for radar and scanning systems
Test and measurement equipment
Commercial and amateur RF exciters
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CLOCK IN
DIFF/SINGLE
SELECT
FSK/BPSK/HOLD
DATA IN
REF
CLK
BUFFER
SYSTEM CLOCK
4× TO 20×
REF CLK
MULTIPLIER
48 48
SYSTEM
CLOCK
MUX
48
3
MUX
DELTA
FREQUENCY
RATE TIMER
MUX
DDS CORE
17 17
14
MUX
12
I
12
Q
INV DIGITAL MULTIPLIERS
SINC
12
FILTER
12-BIT
I
DAC
INV
SINC
FILTER
SYSTEM
CLOCK
12
12-BIT
Q DAC OR
CONTROL
DAC
SYSTEM
CLOCK
12 12
PROGRAMMABLE
AMPLITUDE AND
RATE CONTROL
ANALOG
OUT
DAC RSET
ANALOG
OUT
ANALOG
IN
2 48 SYSTEM 48
CLOCK
DELTA
FREQUENCY
WORD
FREQUENCY
TUNING
WORD 1
48 14
14 12 12
FREQUENCY FIRST 14-BIT SECOND 14-BIT I AND Q 12-BIT 12-BIT DC
TUNING PHASE/OFFSET PHASE/OFFSET AM MODULATION CONTROL
WORD 2
WORD
WORD
COMPARATOR
CLOCK
OUT
BIDIRECTIONAL
INTERNAL/EXTERNAL
I/O UPDATE CLOCK
MODE SELECT
SYSTEM
CLOCK
INT
CK Q
D
EXT
PROGRAMMING REGISTERS
÷2
SYSTEM
CLOCK
AD9854
INTERNAL
PROGRAMMABLE
UPDATE CLOCK
BUS
I/O PORT BUFFERS
OSK
GND
+VS
READ
WRITE SERIAL/
PARALLEL
SELECT
Figure 1.
6-BIT ADDRESS
OR SERIAL
PROGRAMMING
LINES
8-BIT
PARALLEL
LOAD
MASTER
RESET
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2007 Analog Devices, Inc. All rights reserved.






AD9854 Datasheet, Funktion
AD9854
Parameter
Residual Phase Noise
(AOUT = 5 MHz, External Clock = 30 MHz
REFCLK Multiplier Engaged at 10×)
1 kHz Offset
10 kHz Offset
100 kHz Offset
(AOUT = 5 MHz, External Clock = 300 MHz,
REFCLK Multiplier Bypassed)
1 kHz Offset
10 kHz Offset
100 kHz Offset
PIPELINE DELAYS4, 5, 6
DDS Core (Phase Accumulator and
Phase-to-Amp Converter)
Frequency Accumulator
Inverse Sinc Filter
Digital Multiplier
DAC
I/O Update Clock (Internal Mode)
I/O Update Clock (External Mode)
MASTER RESET DURATION
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High-Z Load
Logic 0 Voltage, High-Z Load
Output Power, 50 Ω Load, 120 MHz Toggle Rate
Propagation Delay
Output Duty Cycle Error7
Rise/Fall Times, 5 pF Load
Toggle Rate, High-Z Load
Toggle Rate, 50 Ω Load
Output Cycle-to-Cycle Jitter8
COMPARATOR NARROW-BAND SFDR9
10 MHz (±1 MHz)
10 MHz (±250 MHz)
10 MHz (±50 MHz)
41 MHz (±1 MHz)
41 MHz (±250 MHz)
41 MHz (±50 MHz)
119 MHz (±1 MHz)
119 MHz (±250 MHz)
119 MHz (±50 MHz)
CLOCK GENERATOR OUTPUT JITTER9
5 MHz AOUT
40 MHz AOUT
100 MHz AOUT
Test AD9854ASVZ
AD9854ASTZ
Temp Level Min Typ Max Min Typ Max Unit
25°C V
25°C V
25°C V
140
138
142
140 dBc/Hz
138 dBc/Hz
142 dBc/Hz
25°C V
25°C V
25°C V
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
25°C IV
25°C V
25°C IV
25°C I
25°C IV
Full VI
Full VI
25°C I
25°C IV
25°C I
25°C V
25°C IV
25°C IV
IV
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
25°C V
142 142 dBc/Hz
148 148 dBc/Hz
152 152 dBc/Hz
33
26
16
9
1
2
3
10
33
26
16
9
1
2
3
10
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
3
500
±1 ±5
10 20
3
500
±1 ±5
10 20
pF
μA
mV p-p
3.1
9 11
3
−10 ±1
2
300 350
375 400
3.1
0.16
9 11
3
+10 −10 ±1
2
300 350
375 400
4.0
V
0.16 V
dBm
ns
+10 %
ns
MHz
MHz
4.0 ps rms
84 84 dBc
84 84 dBc
92 92 dBc
76 76 dBc
82 82 dBc
89 89 dBc
73 dBc
73 dBc
83 dBc
23 23 ps rms
12 12 ps rms
7 7 ps rms
Rev. E | Page 6 of 52

6 Page









AD9854 pdf, datenblatt
AD9854
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4 to Figure 9 indicate the wideband harmonic distortion performance of the AD9854 from 19.1 MHz to 119.1 MHz fundamental
output, reference clock = 30 MHz, REFCLK multiplier = 10×. Each graph is plotted from 0 MHz to 150 MHz (Nyquist).
00
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
START 0Hz
15MHz/
STOP 150MHz
Figure 4. Wideband SFDR, 19.1 MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
START 0Hz
15MHz/
STOP 150MHz
Figure 7. Wideband SFDR, 79.1 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
START 0Hz
15MHz/
STOP 150MHz
Figure 5. Wideband SFDR, 39.1 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
START 0Hz
15MHz/
STOP 150MHz
Figure 8. Wideband SFDR, 99.1 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
START 0Hz
15MHz/
STOP 150MHz
Figure 6. Wideband SFDR, 59.1 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
START 0Hz
15MHz/
STOP 150MHz
Figure 9. Wideband SFDR, 119.1 MHz
Rev. E | Page 12 of 52

12 Page





SeitenGesamt 30 Seiten
PDF Download[ AD9854 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
AD9850125 MHz Complete DDS SynthesizerAnalog Devices
Analog Devices
AD9851CMOS 180 MHz DDS/DAC SynthesizerAnalog Devices
Analog Devices
AD9852CMOS 300 MHz Complete-DDSAnalog Devices
Analog Devices
AD9853Programmable Digital OPSK/16-QAM ModulatorAnalog Devices
Analog Devices
AD9854CMOS 300 MHz Quadrature Complete-DDSAnalog Devices
Analog Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche