PDF AD9842A Data sheet ( Hoja de datos )

Número de pieza	AD9842A
Descripción	Complete 20 MSPS CCD Signal Processors
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES 20 MSPS Correlated Double Sampler (CDS) 4 dB ؎ 6 dB 6-Bit Pixel Gain Ampliﬁer (PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Ampliﬁer (VGA) Low Noise Clamp Circuits Analog Preblanking Function 10-Bit (9841) or 12-Bit (9842) 20 MSPS A/D Converter Auxiliary Inputs with VGA and Input Clamp 3-Wire Serial Digital Interface 3 V Single Supply Operation Low Power: 65 mW @ 2.7 V Supply 48-Lead LQFP Package APPLICATIONS Digital Still Cameras Digital Video Camcorders Complete 20 MSPS CCD Signal Processors AD9841A/AD9842A PRODUCT DESCRIPTION The AD9841A and AD9842A are complete analog signal proces- sors for CCD applications. Both products feature a 20 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9841A/AD9842A’s signal chain consists of an input clamp, correlated double sampler (CDS), Pixel Gain Ampliﬁer (PxGA), digitally controlled variable gain ampliﬁer (VGA), black level clamp, and A/D converter. The AD9841A offers 10-bit ADC resolution, while the AD9842A contains a true 12-bit ADC. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input conﬁguration, and power-down modes. The AD9841A and AD9842A operate from a single 3 V power supply, typically dissipate 78 mW, and are packaged in a 48- lead LQFP. CCDIN CLPDM AUX1IN AUX2IN FUNCTIONAL BLOCK DIAGRAM PBLK AVDD AVSS HD VD CLPOB 4dB ؎ 6dB CDS PxGA CLP 6 2:1 MUX BUF CLP AD9841A/AD9842A COLOR STEERING 2:1 MUX 2dB–36dB VGA CLP ADC 10/12 DRVDD DRVSS DOUT OFFSET 10 DAC CONTROL REGISTERS DIGITAL INTERFACE 8 BANDGAP REFERENCE INTERNAL BIAS INTERNAL TIMING VRT VRB CML DVDD DVSS SL SCK SDATA SHP SHD DATACLK PxGA is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 page AD9841A/AD9842A AUX1-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.) Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER Gain Max Input Range 0 1.0 dB V p-p VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain 2.0 1023 0 36 V p-p Steps dB dB Speciﬁcations subject to change without notice. AUX2-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fDATACLK = 20 MHz, unless otherwise noted.) Parameter Min Typ Max Unit POWER CONSUMPTION 60 mW MAXIMUM CLOCK RATE 20 MHz INPUT BUFFER (Same as AUX1-MODE) VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain 2.0 512 0 18 V p-p Steps dB dB ACTIVE CLAMP (AD9841A) Clamp Level Resolution Clamp Level (Measured at ADC Output) Min Clamp Level Max Clamp Level 256 0 63.75 Steps LSB LSB ACTIVE CLAMP (AD9842A) Clamp Level Resolution Clamp Level (Measured at ADC Output) Min Clamp Level Max Clamp Level 256 Steps 0 LSB 255 LSB Speciﬁcations subject to change without notice. REV. 0 –5– 5 Page PIXEL GAIN AMPLIFIER (PxGA) TIMING AD9841A/AD9842A VD FRAME n FRAME n+1 0101... 2323... 0101... 0101... 2323... 0101... HD LINE 0 LINE 1 LINE 2 LINE m–1 LINE m LINE 0 LINE 1 LINE 2 LINE m–1 NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3 Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence LINE m 5 PIXEL MIN VD HD 3ns MIN 3ns MIN SHP PxGA GAIN GAINX GAIN0 GAIN1 GAIN0 GAINX NOTES: 1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES. 2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns. 3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101. 4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323. Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing GAIN2 GAIN3 VD EVEN FIELD ODD FIELD 0101... 2323... 0101... 0101... 2323... 0101... HD LINE 0 LINE 1 LINE 2 LINE m–1 LINE m LINE 0 LINE 1 LINE 2 LINE m–1 NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3 Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence LINE m VD HD SHP 3ns MIN 5 PIXEL MIN 3ns MIN PxGA GAIN GAINX GAIN0 GAIN1 GAIN0 GAINX NOTES: 1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. 2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101. 3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323. Figure 11. PxGA Mode 2 (Interlace) Detailed Timing GAIN2 GAIN3 REV. 0 –11– 11 Page

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