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AD9841A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9841A
Beschreibung Complete 20 MSPS CCD Signal Processors
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 23 Seiten
AD9841A Datasheet, Funktion
a
FEATURES
20 MSPS Correlated Double Sampler (CDS)
4 dB ؎ 6 dB 6-Bit Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit (9841) or 12-Bit (9842) 20 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 65 mW @ 2.7 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras
Digital Video Camcorders
Complete 20 MSPS
CCD Signal Processors
AD9841A/AD9842A
PRODUCT DESCRIPTION
The AD9841A and AD9842A are complete analog signal proces-
sors for CCD applications. Both products feature a 20 MHz
single-channel architecture designed to sample and condition
the outputs of interlaced and progressive scan area CCD arrays.
The AD9841A/AD9842A’s signal chain consists of an input
clamp, correlated double sampler (CDS), Pixel Gain Amplifier
(PxGA), digitally controlled variable gain amplifier (VGA),
black level clamp, and A/D converter. The AD9841A offers 10-bit
ADC resolution, while the AD9842A contains a true 12-bit
ADC. Additional input modes are provided for processing analog
video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
The AD9841A and AD9842A operate from a single 3 V power
supply, typically dissipate 78 mW, and are packaged in a 48-
lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
FUNCTIONAL BLOCK DIAGRAM
PBLK
AVDD
AVSS
HD
VD
CLPOB
4dB ؎ 6dB
CDS
PxGA
CLP
6
2:1
MUX
BUF
CLP
AD9841A/AD9842A
COLOR
STEERING
2:1
MUX
2dB–36dB
VGA
CLP
ADC
10/12
DRVDD
DRVSS
DOUT
OFFSET
10 DAC
CONTROL
REGISTERS
DIGITAL
INTERFACE
8
BANDGAP
REFERENCE
INTERNAL
BIAS
INTERNAL
TIMING
VRT
VRB
CML
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
PxGA is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001






AD9841A Datasheet, Funktion
AD9841A/AD9842A
TIMING SPECIFICATIONS (CL = 20 pF, fSAMP = 20 MHz, CCD-Mode Timing in Figures 5 and 6, AUX-Mode Timing in Figure 7.
Serial Timing in Figures 2124.)
Parameter
Symbol
Min
Typ Max
Unit
SAMPLE CLOCKS
DATACLK, SHP, SHD Clock Period
DATACLK Hi/Low Pulsewidth
SHP Pulsewidth
SHD Pulsewidth
CLPDM Pulsewidth
CLPOB Pulsewidth1
SHP Rising Edge to SHD Falling Edge
SHP Rising Edge to SHD Rising Edge
Internal Clock Delay
Inhibited Clock Period
DATA OUTPUTS
Output Delay
Output Hold Time
Pipeline Delay
tCONV
tADC
tSHP
tSHD
tCDM
tCOB
tS1
tS2
tID
tINH
tOD
tH
48
20
7
7
4
2
0
20
10
7.0
50
25
12.5
12.5
10
20
12.5
25
3.0
14.5 16
7.6
9
ns
ns
ns
ns
Pixels
Pixels
ns
ns
ns
ns
ns
ns
Cycles
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
fSCLK
tLS
tLH
tDS
tDH
tDV
10
10
10
10
10
10
NOTES
1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.
Specifications subject to change without notice.
MHz
ns
ns
ns
ns
ns
ABSOLUTE MAXIMUM RATINGS
Parameter
With
Respect
To Min Max
Unit
AVDD1, AVDD2
DVDD1, DVDD2
DRVDD
Digital Outputs
SHP, SHD, DATACLK
CLPOB, CLPDM, PBLK
SCK, SL, SDATA
VRT, VRB, CMLEVEL
BYP1-4, CCDIN
Junction Temperature
Lead Temperature
(10 sec)
AVSS
DVSS
DRVSS
DRVSS
DVSS
DVSS
DVSS
AVSS
AVSS
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 +3.9
V
–0.3 DRVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 DVDD + 0.3 V
–0.3 AVDD + 0.3 V
–0.3 AVDD + 0.3 V
150 °C
300 °C
ORDERING GUIDE
Model
Temperature
Range
AD9841AJST –20°C to +85°C
AD9842AJST –20°C to +85°C
Package
Description
Thin Plastic
Quad Flatpack
(LQFP)
Thin Plastic
Quad Flatpack
(LQFP)
Package
Option
ST-48
ST-48
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package
θJA = 92°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9841A/AD9842A features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. 0

6 Page









AD9841A pdf, datenblatt
AD9841A/AD9842A
VD LINE n
LINE n+1
012012012...
...01201
012012012...
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2
Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
5 PIXEL MIN
VD
HD
SHP
5 PIXEL MIN
3ns MIN
PxGA GAIN
GAINX GAIN0
GAIN1 GAIN2 GAIN0
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.
Figure 13. PxGA Mode 3 (3-Color) Detailed Timing
GAINX
GAIN0
GAIN1
VD LINE n
LINE n+1
01230123012...
...01230
012301230123...
HD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
VD
HD
SHP
5 PIXEL MIN
5 PIXEL MIN
3ns MIN
PxGA GAIN
GAINX GAIN0
GAIN1 GAIN2
GAIN0
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.
Figure 15. PxGA Mode 4 (4-Color) Detailed Timing
GAINX
GAIN0
GAIN1
–12–
REV. 0

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