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AD9840A Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9840A
Beschreibung Complete 10-Bit 40 MSPS CCD Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD9840A Datasheet, Funktion
a
FEATURES
40 MSPS Correlated Double Sampler (CDS)
4 dB ؎ 6 dB Variable CDS Gain with 6-Bit Resolution
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Clamp Circuits
Analog Preblanking Function
10-Bit 40 MSPS A/D Converter
Auxiliary Inputs with VGA and Input Clamp
3-Wire Serial Digital Interface
3 V Single Supply Operation
Low Power: 155 mW @ 3.0 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Video Camcorders
Digital Still Cameras
Industrial Imaging
Complete 10-Bit 40 MSPS
CCD Signal Processor
AD9840A
PRODUCT DESCRIPTION
The AD9840A is a complete analog signal processor for CCD
applications. It features a 40 MHz single-channel architecture
designed to sample and condition the outputs of interlaced and
progressive scan area CCD arrays. The AD9840A’s signal chain
consists of an input clamp, correlated double sampler (CDS),
digitally controlled variable gain amplifier (VGA), black level
clamp, and 10-bit A/D converter. Additional input modes are
provided for processing analog video signals.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjustment,
black level adjustment, input configuration, and power-down modes.
The AD9840A operates from a 3 V power supply, typically
dissipates 155 mW, and is packaged in a 48-lead LQFP.
CCDIN
CLPDM
AUX1IN
AUX2IN
PBLK
FUNCTIONAL BLOCK DIAGRAM
AVDD
AVSS
CLPOB
4dB؎6dB
CDS
CLP
2:1
MUX
BUF
CLP
AD9840A
2dB TO 36dB
2:1
MUX
VGA
CLP
10-BIT
ADC
10
10
6
INTERNAL
REGISTERS
OFFSET
DAC
8
BANDGAP
REFERENCE
INTERNAL
BIAS
DIGITAL
INTERFACE
INTERNAL
TIMING
DRVDD
DRVSS
DOUT
VRT
VRB
CML
DVDD
DVSS
SL SCK SDATA
SHP SHD DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






AD9840A Datasheet, Funktion
AD9840A
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
DRVSS 1
DRVSS 2
(LSB) D0 3
D1 4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 10
D8 11
(MSB) D9 12
PIN 1
IDENTIFIER
AD9840A
TOP VIEW
(Not to Scale)
36 AUX1IN
35 AVSS
34 AUX2IN
33 AVDD2
32 BYP4
31 NC
30 CCDIN
29 BYP2
28 BYP1
27 AVDD1
26 AVSS
25 AVSS
NC = NO CONNECT 13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin Number
Name
Type
Description
1, 2
3–12
13
14
15, 18, 24, 41
16
17
19
20
21
22
23
25, 26, 35
27
28
29
30
31
32
33
34
36
37
38
39
40
42
43
44
45
46
47
48
DRVSS
D0–D9
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
PBLK
CLPOB
SHP
SHD
CLPDM
AVSS
AVDD1
BYP1
BYP2
CCDIN
NC
BYP4
AVDD2
AUX2IN
AUX1IN
CML
VRT
VRB
DVDD2
THREE-STATE
NC
STBY
NC
SL
SDATA
SCK
P
DO
P
P
P
DI
P
DI
DI
DI
DI
DI
P
P
AO
AO
AI
NC
AO
P
AI
AI
AO
AO
AO
P
DI
NC
DI
NC
DI
DI
DI
Digital Driver Ground
Digital Data Outputs
Digital Output Driver Supply
Digital Output Driver Ground
Digital Ground
Digital Data Output Latch Clock
Digital Supply
Preblanking Clock Input
Black Level Clamp Clock Input
CDS Sampling Clock for CCD’s Reference Level
CDS Sampling Clock for CCD’s Data Level
Input Clamp Clock Input
Analog Ground
Analog Supply
Internal Bias Level. Decoupling
Internal Bias Level Decoupling
Analog Input for CCD Signal
Leave Floating or Decouple to Ground with 0.1 F
Internal Bias Level Decoupling
Analog Supply
Analog Input
Analog Input
Internal Bias Level Decoupling
A/D Converter Top Reference Voltage Decoupling
A/D Converter Bottom Reference Voltage Decoupling
Digital Supply
Digital Output Disable. Active High
May be tied High or Low. Should not be left floating.
Standby Mode, Active High. Same as Serial Interface Standby Mode
Internally Not Connected. May be tied high or low
Serial Digital Interface Load Pulse
Serial Digital Interface Data
Serial Digital Interface Clock
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
–6– REV. 0

6 Page









AD9840A pdf, datenblatt
AD9840A
together with CLPOB or separately. The CLPDM pulse should
be a minimum of four pixels wide.
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with the typical 4 dB gain from the CDS stage, the
total gain range for the AD9840A is 6 dB to 40 dB. A gain of 6 dB
will match a 1 V input signal with the ADC full-scale range of 2 V.
When compared to 1 V full-scale systems (such as ADI’s AD9803),
the equivalent gain range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-
dB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Code Range Gain Equation (dB)
0–511
512–1023
Gain = 20 log10 ([658 + code]/[658 – code]) – 0.35
Gain = (0.0354)(code) – 0.35
Using these two equations, the actual gain of the AD9840A can
be accurately predicted to within ؎0.5 dB. As shown in the CCD-
Mode Specifications, only the VGA gain range from 2 dB to 36 dB
is specified. This corresponds to a VGA gain code range of 91 to
1023. The Gain Accuracy specifications also include a CDS gain
of 4 dB, for a total gain range of 6 dB to 40 dB.
36
30
24
18
12
6
0
0 127 255 383 511 639 767 895 1023
VGA GAIN REGISTER CODE
Figure 13. VGA Gain Curve (Gain from CDS Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 64 LSB may be pro-
grammed, with 8-bit resolution. The resulting error signal is
filtered to reduce noise, and the correction value is applied to
the ADC input through a D/A converter. Normally, the optical
black clamp loop is turned on once per horizontal line, but this
loop can be updated more slowly to suit a particular application.
If external digital clamping is used during the post processing, the
AD9840A’s optical black clamping may be disabled using Bit D5
in the Operation Register (see Serial Interface Timing and
Internal Register Description section). When the loop is dis-
abled, the Clamp Level Register may still be used to provide
programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the loop’s ability to
track low-frequency variations in the black level will be reduced.
A/D Converter
The AD9840A uses a high-performance ADC architecture,
optimized for high speed and low power. Differential nonlin-
earity (DNL) performance is typically better than 0.5 LSB.
Instead of the 1 V full-scale range used by the earlier AD9801 and
AD9803 products from Analog Devices, the AD9840A’s ADC
uses a 2 V input range. Better noise performance results from
using a larger ADC full-scale range.
AUX1-Mode
For applications that do not require CDS, the AD9840A can be
configured to sample ac-coupled waveforms. Figure 14 shows the
circuit configuration for using the AUX1 channel input (Pin
36). A single 0.1 µF ac-coupling capacitor is needed between the
input signal driver and the AUX1IN pin. An on-chip dc-bias
circuit sets the average value of the input signal to approxi-
mately 0.4 V, which is referenced to the midscale code of the ADC.
The VGA gain register provides a gain range of 0 dB to 36 dB
in this mode of operation (see VGA Gain Curve, Figure 13).
The VGA gains up the signal level with respect to the 0.4 V bias
level. Signal levels above the bias level will be further increased
to a higher ADC code, while signal levels below the bias level
will be further decreased to a lower ADC code.
AUX2-Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 15 shows the circuit
configuration for using the AUX2 channel input (Pin 34). An
external 0.1 µF blocking capacitor is used with the on-chip
video clamp circuit, to level-shift the input signal to a desired
reference level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the input
signal to be equal to the value programmed into the Clamp Level
register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VIII.)
–12–
REV. 0

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