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PDF AD9834 Data sheet ( Hoja de datos )
| Número de pieza | AD9834 | |
| Descripción | 75 MHz Complete DDS | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
20 mW Power, 2.3 V to 5.5 V,
75 MHz Complete DDS
AD9834
FEATURES
Narrow-band SFDR >72 dB
2.3 V to 5.5 V power supply
Output frequency up to 37.5 MHz
Sine output/triangular output
On-board comparator
3-wire SPI® interface
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits; with a 75 MHz clock
rate, resolution of 0.28 Hz can be achieved. Similarly, with a 1 MHz
clock rate, the AD9834 can be tuned to 0.004 Hz resolution.
Frequency and phase modulation are affected by loading registers
through the serial interface and toggling the registers using
software or the FSELECT pin and PSELECT pin, respectively.
Extended temperature range: −40°C to +105°C
Power-down option
20 mW power consumption at 3 V
20-lead TSSOP
APPLICATIONS
The AD9834 is written to using a 3-wire serial interface. This
serial interface operates at clock rates up to 40 MHz and is
compatible with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V.
The analog and digital sections are independent and can be run
Frequency stimulus/waveform generation
from different power supplies, for example, AVDD can equal
Frequency phase tuning and modulation
5 V with DVDD equal to 3 V.
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
detection
Test and medical equipment
GENERAL DESCRIPTION
The AD9834 is a 75 MHz low power DDS device capable of
The AD9834 has a power-down pin (SLEEP) that allows
external control of the power-down mode. Sections of the
device that are not being used can be powered down to
minimize the current consumption. For example, the DAC can
be powered down when a clock output is being generated.
The part is available in a 20-lead TSSOP.
producing high performance sine and triangular outputs. It also
has an on-board comparator that allows a square wave to be
produced for clock generation. Consuming only 20 mW of power
at 3 V makes the AD9834 an ideal candidate for power-sensitive
applications.
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DGND
DVDD CAP/2.5V
REFOUT FS ADJUST
MCLK
FSELECT
28-BIT FREQ0
REG
28-BIT FREQ1
REG
REGULATOR
VCC
2.5V
ON-BOARD
REFERENCE
MUX
PHASE
ACCUMULATOR
(28-BIT)
12
Σ
SIN
ROM
MUX
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDED
BY 2
FULL-SCALE
CONTROL
10-BIT
DAC
MSB
COMP
IOUT
IOUTB
16-BIT CONTROL
REGISTER
MUX
SIGN BIT OUT
SERIAL INTERFACE
AND
CONTROL LOGIC
COMPARATOR
VIN
AD9834
FSYNC SCLK SDATA
PSELECT
SLEEP RESET
Figure 1.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2003–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD9834
Parameter2
POWER SUPPLIES
AVDD
DVDD
IAA 6
IDD6
B Grade
C Grade
IAA + IDD6
B Grade
C Grade
Low Power Sleep Mode
B Grade
C Grade
Grade B, Grade C1
Min Typ
Max Unit Test Conditions/Comments
2.3
2.3
3.8
5.5 V
fMCLK = 75 MHz, fOUT = fMCLK/4096
5.5 V
5 mA
2.0 3
mA IDD code dependent (see Figure 8)
2.7 3.7 mA IDD code dependent (see Figure 8)
5.8 8
mA
6.5 8.7 mA
0.5 mA DAC powered down, MCLK running
0.6 mA DAC powered down, MCLK running
1 B grade: MCLK = 50 MHz; C grade: MCLK = 75 MHz. For specifications that do not specify a grade, the value applies to both grades.
2 Operating temperature range is as follows: B, C versions: −40°C to +105°C, typical specifications are at 25°C.
3 For compliance, with specified load of 200 Ω, IOUT full scale should not exceed 4 mA.
4 Guaranteed by design.
5 Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
6 Measured with the digital inputs static and equal to 0 V or DVDD.
100nF
10nF
RSET
6.8kΩ
CAP/2.5V
REFOUT
FS ADJUST
REGULATOR
ON-BOARD
REFERENCE
FULL-SCALE COMP
CONTROL
AVDD
10nF
AD9834
12
SIN
ROM
10-BIT DAC IOUT
RLOAD
200Ω
Figure 2. Test Circuit Used to Test the Specifications
20pF
Rev. D | Page 5 of 32
5 Page 
Data Sheet
1000
950
900
850
800
750
700
650
600
550
500
–40
2.3V
5.5V
25
TEMPERATURE (°C)
Figure 13. Wake-Up Time vs. Temperature
105
1.250
1.225
1.200
1.175
1.150
1.125
1.100
–40
UPPER RANGE
LOWER RANGE
25
TEMPERATURE (°C)
Figure 14. VREFOUT vs. Temperature
105
–100
–110
AVDD = DVDD = 5V
TA = 25°C
–120
–130
–140
–150
–160
100
1k 10k
FREQUENCY (Hz)
100k 200k
Figure 15. Output Phase Noise, fOUT = 2 MHz, MCLK = 50 MHz
AD9834
0.20
0.18 DVDD = 3.3V
0.16 DVDD = 2.3V
0.14
DVDD = 5.5V
0.12
0.10
0.08
0.06
0.04
0.02
0
–40 –20
0 20 40 60
TEMPERATURE (°C)
80
Figure 16. SIGN BIT OUT Low Level, ISINK = 1 mA
100
5.5
DVDD = 5.5V
5.0
4.5 DVDD = 4.5V
4.0
3.5
DVDD = 3.3V
3.0
DVDD = 2.7V
2.5
2.0 DVDD = 2.3V
1.5
–40
–20
0 20 40 60
TEMPERATURE (°C)
80 100
Figure 17. SIGN BIT OUT High Level, ISINK = 1 mA
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
RWB 100
VWB 30
FREQUENCY (Hz)
100k
ST 100 SEC
Figure 18. fMCLK = 10 MHz; fOUT = 2.4 kHz, Frequency Word = 000FBA9
Rev. D | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9834.PDF ] | |
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