PDF AD9831 Data sheet ( Hoja de datos )

Número de pieza	AD9831
Descripción	CMOS Complete DDS
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de AD9831 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas
No Preview Available ! a DIRECT DIGITAL SYNTHESIZER, WAVEFORM GENERATOR FEATURES 3 V/5 V Power Supply 25 MHz Speed On-Chip SINE Look-Up Table On-Chip 10-Bit DAC Parallel Loading Powerdown Option 72 dB SFDR 125 mW (5 V) Power Consumption 40 mW (3 V) Power Consumption 48-Pin LQFP APPLICATIONS DDS Tuning Digital Demodulation MCLK FSELECT FREQ0 REG FREQ1 REG AD9831 GENERAL DESCRIPTION This DDS device is a numerically controlled oscillator employ- ing a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 25 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the parallel microprocessor interface. A powerdown pin allows external control of a powerdown mode. The part is available in a 48-pin LQFP package. Similar DDS products can be found at http://www.analog.com/DDS. FUNCTIONAL BLOCK DIAGRAM DVDD DGND AVDD AGND REFOUT FS ADJUST REFIN ON-BOARD REFERENCE FULL-SCALE CONTROL COMP MUX PHASE ACCUMULATOR (32-BIT) 12 Σ SIN ROM 10-BIT DAC IOUT PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG MUX PARALLEL REGISTER TRANSFER CONTROL MPU INTERFACE AD9831 SLEEP RESET D0 D15 WR A0 A1 A2 PSEL0 PSEL1 REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 2011 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 1 page AD9831 PIN DESCRIPTION Mnemonic Function POWER SUPPLY AVDD Positive power supply for the analog section. A 0.1 µF decoupling capacitor should be connected between AVDD and AGND. AVDD can have a value of +5 V ± 10% or +3.3 V ± 10%. AGND Analog Ground. DVDD Positive power supply for the digital section. A 0.1 µF decoupling capacitor should be connected between DVDD and DGND. DVDD can have a value of +5 V ± 10% or +3.3 V ± 10%. DGND Digital Ground. ANALOG SIGNAL AND REFERENCE IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. FS ADJUST REFIN Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUTFULL-SCALE = 12.5 × VREFIN/RSET VREFIN = 1.21 V nominal, RSET = 3.9 kΩ typical Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831 accepts a reference of 1.21 V nominal. REFOUT Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND. COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic capacitor should be connected between COMP and AVDD. DIGITAL INTERFACE AND CONTROL MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loaded into the AD9831 on the rising edge of the WR pulse. This data is then loaded into the destination register on the MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR rising edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination register will be loaded on the next MCLK rising edge. D0–D15 Data Bus, Digital Inputs for destination registers. A0–A2 Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to be written. PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. SLEEP Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks are disabled and the DAC’s current sources and REFOUT are turned off. The AD9831 is re-enabled by taking SLEEP high. RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog output of midscale. REV. B –5– 5 Page AD9831 DSP and MPU Interfacing The AD9831 has a parallel interface, with 16 bits of data being loaded during each write cycle. The frequency or phase registers are loaded by asserting the WR signal. The destination register for the 16 bit data is selected using the address inputs A0, A1 and A2. The phase registers are 12 bits wide so, only the 12 LSBs need to be valid—the 4 MSBs of the 16 bit word do not have to contain valid data. Data is loaded into the AD9831 by pulsing WR low, the data being latched into the AD9831 on the rising edge of WR. The values of inputs A0, A1 and A2 are also latched into the AD9831 on the WR rising edge. The appropriate destination register is updated on the next MCLK rising edge. If the WR rising edge coincides with the MCLK rising edge, there is an uncertainty of one MCLK cycle regarding the loading of the destination register—the destination register may be loaded immediately or the destination register may be updated on the next MCLK rising edge. To avoid any uncertainty, the times listed in the specifications should be complied with. FSELECT, PSEL0 and PSEL1 are sampled on the MCLK rising edge. Again, these inputs should be valid when an MCLK rising edge occurs as there will be an uncertainty of one MCLK cycle introduced otherwise. When these inputs change value, there will be a pipeline delay before control is transferred to the selected register—there will be a pipeline delay before the analog output is controlled by the selected register. There is a similar delay when a new word is written to a register. PSEL0, PSEL1, FSELECT and WR have latencies of six MCLK cycles. The flow chart in Figure 22 shows the operating routine for the AD9831. When the AD9831 is powered up, the part should be reset using RESET. This will reset the phase accumulator to zero so that the analog output is at midscale. RESET does not reset the phase and frequency registers. These registers will contain invalid data and, therefore, should be set to zero by the user. The registers to be used should be loaded, the analog output being fMCLK/232 × FREG where FREG is the value loaded into the selected frequency register. This signal will be phase shifted by the amount specified in the selected phase register (2π/4096 × PHASEREG where PHASEREG is the value contained in the selected phase register). When FSELECT, PSEL0 and PSEL1 are programmed, there will be a pipeline delay of approximately 6 MCLK cycles before the analog output reacts to the change on these inputs. RESET DATA WRITE FREG<0, 1> = 0 PHASEREG<0, 1, 2, 3> = 0 DATA WRITE FREG<0> = fOUT0/fMCLK232 FREG<1> = fOUT1/fMCLK232 PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3> SELECT DATA SOURCES SET FSELECT SET PSEL0, PSEL1 WAIT 6 MCLK CYCLES DAC OUTPUT VOUT = VREFIN6.25ROUT/RSET(1 + SIN(2π(FREGfMCLK*t/232 + PHASEREG/212))) CHANGE FSELECT YES CHANGE PHASE? NO NO CHANGE FOUT? YES NO CHANGE FREG? NO CHANGE PHASEREG? YES YES CHANGE PSEL0, PSEL1 Figure 22. Flow Chart for AD9831 Initialization and Operation REV. B –11– 11 Page

Páginas	Total 16 Páginas
PDF Descargar	[ Datasheet AD9831.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AD9830	CMOS Complete DDS	Analog Devices
AD9831	CMOS Complete DDS	Analog Devices
AD9832	CMOS Complete DDS	Analog Devices
AD9833	Programmable Waveform Generator	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar