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AD9821 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9821
Beschreibung Complete 12-Bit 40 MSPS Imaging Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD9821 Datasheet, Funktion
FEATURES
Differential Sensor Input with 1 V p-p Input Range
0 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
Low Noise Optical Black Clamp Circuit
Analog Preblanking Function
12-Bit 40 MSPS A/D Converter (ADC)
3-Wire Serial Digital Interface
3 V Single-Supply Operation
Low Power: 150 mW @ 3 V Supply
48-Lead LQFP Package
APPLICATIONS
Digital Still Cameras Using CMOS Imagers
Industrial/Scientific Imaging
Complete 12-Bit 40 MSPS
Imaging Signal Processor
AD9821
GENERAL DESCRIPTION
The AD9821 is a complete analog signal processor for imaging
applications that do not require Correlated Double Sampling
(CDS). It features a 40 MHz single-channel architecture designed
to sample and condition the outputs of CMOS imagers and CCD
arrays already containing on-chip CDS. The AD9821’s signal
chain consists of a differential input sample-and-hold amplifier
(SHA), digitally controlled variable gain amplifier (VGA), black
level clamp, and a 12-bit ADC.
The internal registers are programmed through a 3-wire serial
digital interface. Programmable features include gain adjust-
ment, black level adjustment, and power-down modes.
The AD9821 operates from a single 3 V power supply, typically
dissipates 150 mW, and is packaged in a 48-lead LQFP.
VIN+
VIN–
BYP1
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
VRT VRB
AD9821
+
SHA
0dB ~ 36dB
VGA
BAND GAP
REFERENCE
12-BIT
ADC
PBLK
12
DRVDD
DRVSS
DOUT
10 CLP
INTERNAL
REGISTERS
DIGITAL
INTERFACE
8 BLK CLAMP
LEVEL
CLPOB
DVDD
DVSS
SL SCK SDATA
DATACLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002






AD9821 Datasheet, Funktion
AD9821
DEFINITIONS OF SPECIFICATIONS
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus, every
code must have a finite width. No missing codes guaranteed to
12-bit resolution indicates that all 4096 codes, respectively,
must be present over all operating conditions.
Peak Nonlinearity
Peak nonlinearity, a full signal chain specification, refers to the
peak deviation of the output of the AD9821 from a true straight
line. The point used as “zero scale” occurs 1/2 LSB before the
first code transition. “Positive full scale” is defined as a Level 1,
1/2 LSB beyond the last code transition. The deviation is mea-
sured from the middle of each particular output code to the true
straight line. The error is then expressed as a percentage of the
2 V ADC full-scale signal. The input signal is always appropriately
gained up to fill the ADC’s full-scale range.
Total Output Noise
The rms output noise is measured using histogram techniques.
The standard deviation of the ADC output codes is calculated
in LSB and represents the rms noise level of the total signal
chain at the specified gain setting. The output noise can be
converted to an equivalent voltage using the relationship 1 LSB =
(ADC Full Scale/2N codes) when N is the bit resolution of the ADC.
For the AD9821, 1 LSB is 500 µV.
Power Supply Rejection (PSR)
The PSR is measured with a step change applied to the supply
pins. This represents a very high frequency disturbance on the
AD9821’s power supply. The PSR specification is calculated
from the change in the data outputs for a given step change in
the supply voltage.
Internal Delay for SHA
The internal delay (also called aperture delay) is the time delay
that occurs from when the sampling edge is applied to the AD9821
until the actual sample of the input signal is held. The DATACLK
samples the input signal during the transition from low to high,
so the internal delay is measured from each clock’s rising edge
to the instant the actual internal sample is taken.
EQUIVALENT INPUT CIRCUITS
DVDD
330
AVDD
60
DVSS
Figure 1. Digital Inputs— DATACLK, CLPOB, PBLK, SCK, SL
DVDD
DRVDD
DATA
ACVSS
ACVSS
Figure 3. VIN+ and VIN– (Pins 30 and 31)
THREE-
STATE
DOUT
DVDD
DATA IN
DATA OUT
DVDD
330
DVSS
DRVSS
Figure 2. Data Outputs—D0–D11
RNW
–6–
DVSS
DVSS
Figure 4. SDATA (Pin 47)
DVSS
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AD9821 pdf, datenblatt
AD9821
Variable Gain Amplifier
The VGA stage provides a gain range of 0 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface. A
minimum gain of 6 dB is needed to match a 1 V input signal with
the ADC full-scale range of 2 V. When compared to 1 V full-scale
systems, the equivalent gain range is –6 dB to +30 dB.
The VGA gain curve follows a “linear-in-dB” characteristic.
The exact VGA gain can be calculated for any Gain Register
value by using the equation:
Gain(dB) = (0.0351 × Code)
where the code range is 0 to 1023.
36
30
24
18
12
6
0
0 127 255 383 511 639 767 895 1023
VGA GAIN REGISTER CODE
Figure 11. VGA Gain Curve
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference selected by the user in the Clamp Level
Register. Any value between 0 LSB and 255 LSB may be
programmed using the 8-bit Clamp Level Register. The resulting
error signal is filtered to reduce noise, and the correction value is
applied to the ADC input through a D/A converter. Normally, the
optical black clamp loop is turned on once per horizontal line, but
this loop can be updated more slowly to suit a particular
application. If external digital clamping is used during the post-
processing, the AD9821 optical black clamping may be disabled
using Bit D5 in the Operation Register (see Internal Register
Map and Serial Interface Timing section). When the loop is
disabled, the Clamp Level Register may still be used to provide
programmable offset adjustment.
Horizontal timing is shown in Figure 9. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide. Shorter pulsewidths may be used, but the ability to
track low frequency variations in the black level will be reduced.
As discussed in the Differential Input SHA section, the CLPOB
loop is capable of correcting for an offset difference between the
VIN+ and VIN– inputs. Because the clamp is located after the
VGA gain stage, the clamp will be most limited when the VGA
gain is at its maximum value. Under these conditions, the OB
clamp loop correction range is restricted to ± 30 mV offset
between the VIN+ and VIN– inputs. At minimum VGA gain,
the offset correction range increases to ± 250 mV of offset. If the
OB clamp loop’s correction range is exceeded, then the black
level at the output of the AD9821 will increase and further
correction will be necessary. As mentioned previously, it is also
possible to disable the AD9821’s OB clamp loop.
A/D Converter (ADC)
The AD9821 uses high performance ADC architecture, opti-
mized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB, as shown in
TPC 2. Instead of the 1 V full-scale range used by the earlier
AD9801 and AD9803 products from Analog Devices, the
AD9821’s ADC uses a 2 V input range. Better noise performance
results from using a larger ADC full-scale range (see TPC 3).
–12–
REV. 0

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