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AD9816 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9816
Beschreibung Complete 12-Bit 6 MSPS CCD/CIS Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 16 Seiten
AD9816 Datasheet, Funktion
a
FEATURES
12-Bit 6 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel or 1-Channel Operation
Correlated Double Sampling
8-Bit Programmable Gain
8-Bit Offset Adjustment
PGA Output Monitor
Input Clamp Circuitry
Internal Voltage Reference
3-Wire Serial Interface
+3.3 V/+5 V Digital Output Compatibility
44-Lead MQFP Package
Low Power CMOS: 420 mW Typ
Complete 12-Bit 6 MSPS
CCD/CIS Signal Processor
AD9816
PRODUCT DESCRIPTION
The AD9816 is a complete analog signal processor for CCD
and CIS applications. Included is all the necessary circuitry to
perform three-channel conditioning and sampling for a variety
of imaging applications.
The signal chain consists of an input clamp, correlated double
sampler (CDS), offset adjust DAC, programmable gain ampli-
fier and a 12-bit A/D converter. The CDS and input clamp may
be disabled for CIS applications.
The internal registers are programmed using a 3-wire serial
interface and provide adjustment of the gain, offset and operat-
ing mode.
The AD9816 operates from a +5 V supply, typically consumes
420 mW of power and is packaged in a 44-lead MQFP.
VINR
VING
VINB
OFFSET
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS CAPT CAPB CML PGAOUT VREF DVDD DVSS DRVDD DRVSS
؎100mV
CLAMP/CDS
+
DAC
1X–6X
PGA
AD9816
BANDGAP
REFERENCE
CLAMP/CDS
CLAMP/CDS
+
DAC
PGA
PGA
+
DAC
8
OFFSET
REGISTERS
MUX
MUX
REGISTER
CONFIGURATION
REGISTER
8
RR
GAIN
G G REGISTERS
BB
12-BIT 12
ADC
DIGITAL
CONTROL
PORT
OEB
DOUT
11:0
SCLK
SLOAD
SDATA
CDSCLK1 CDSCLK2 ADCCLK
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998






AD9816 Datasheet, Funktion
AD9816
ABSOLUTE MAXIMUM RATINGS*
Parameter
With
Respect
To Min
Max
Units
VIN, VREF
AVSS –0.3 AVDD + 0.3 V
PGA Outputs
AVSS –0.3 AVDD + 0.3 V
Clock Inputs
DVSS –0.3 DVDD + 0.3 V
AVDD
AVSS –0.5 +6.5
V
DVDD
DVSS –0.5 +6.5
V
DRVDD
DRVSS –0.5 +6.5
V
AVSS
DVSS –0.3 +0.3
V
Digital Outputs
DRVSS –0.3 DRVDD + 0.3 V
Digital Inputs
DVSS –0.3 DVDD + 0.3 V
Junction Temperature
+150
°C
Storage Temperature
–65 +150
°C
Lead Temperature
(10 sec)
+300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Model
AD9816JS
AD9816JS-80010
AD9816-EB
Temperature
Range
0°C to +70°C
0°C to +70°C
ORDERING GUIDE
Package
Description
44-Lead MQFP (Metric) Plastic Quad Flatpack
44-Lead MQFP (Metric) Plastic Quad Flatpack
Evaluation Board
Package
Option
S-44
S-44
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9816 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6– REV. A

6 Page









AD9816 pdf, datenblatt
AD9816
Line Clamp
If a line clamp technique is implemented (see Figure 5 for
timing), the value of CIN should be increased to more than
1200 pF. The main requirement for line clamp is to keep the
signal droop below 1 LSB across a scanned line. For example, if
a CCD with 5400 effective pixels is clocked at 2 MHz, then
t = 2.7 ms. One LSB at 12 bits with a 3 V full scale is 732 µV.
Rearranging the above droop equation:
CMIN
=
iBIAS
dV
×t
In this case, CMIN = 37 nF, and a convenient standard value of
0.047 µF will be adequate.
SHA Mode Operation
When the AD9816 is configured for SHA mode operation, the
OFFSET pin functions as an offset adjustment input. Figure
15 shows a simplified diagram of the AD9816’s inputs when SHA
mode is selected. A positive dc voltage may be applied to OFFSET
which will be subtracted from all three input channels in the
input stage of the AD9816. The maximum input voltage to the
analog input pins or the OFFSET pin in SHA mode is 3 V.
The OFFSET feature is provided to allow coarse offset adjust-
ment of the input signal. If the signal is sampled with respect to
ground, any positive offset on the input signal will subtract from
the dynamic range of the ADC. For example, an input signal
that spans from 1.5 V to 2.5 V cannot utilize all of the available
dynamic range, using either the 1.5 V or 3 V span. However, by
applying a dc value of 1.5 V to the OFFSET pin, the input
signal will be level-shifted down to 0 V to 1 V. This would
allow the use of the 3 V span and a PGA gain of three to use
the entire ADC dynamic range.
If no dc offset adjustment is desired, the OFFSET pin should
be grounded. The input signal will be sampled with respect to
ground.
VINR
VING
VINB
OFFSET
AD9816
BUFFER
BUFFER
12k
BUFFER
SHA
SHA
SHA
CDSCLK1 CDSCLK2
Figure 15. SHA Mode Input Circuit
Programmable Gain Amplifiers
The AD9816 has three programmable amplifiers, one for each
channel. The gain is variable from 1 V/V (0 dB) to 5.98 V/V
(15.5 dB) in 256 increments. Figure 16 shows the PGA gain
transfer function. The gain of the PGA can be calculated ac-
cording to the equation:
PGA
Gain
=
1+
Gain Code
 51.2 
6
5
4
3
2
1
0 51 102 153 204 255
GAIN REGISTER CODE – Decimal
Figure 16. PGA Gain Transfer Function
The analog outputs of the three PGAs are multiplexed to the input
of the 12-bit ADC. The differential output of the MUX is also
buffered and externally available at Pins 43 and 44 (PGAOUT_C
and PGAOUT_T, respectively). The timing diagrams, Fig-
ures 1 through 4, show the timing relationships between the
analog inputs, CDSCLK2, ADCCLK, and PGAOUT_T and
PGAOUT_C. The CDSCLK2 pulse resets the outputs of all
three PGAs to an internal bias level. The first rising edge of
ADCCLK after the rising edge of CDSCLK2 will switch the
MUX to the red PGA output. The second ADCCLK rising
edge switches the MUX to the green PGA output, and the third
rising edge switches the MUX to the blue PGA output.
PGA Outputs
The PGAOUT_T and PGAOUT_C signals represent the differ-
ential input to the ADC, and are complementary. Both signals
will reset to 3.5 V while CDSCLK2 is high. The voltage swing
of each output is equal to one-half of the ADC’s full-scale volt-
age, centered at 3.5 V. Table V shows the relationship between
the analog input voltage, the PGA output voltage and the ADC
input voltage.
Figure 18 shows the PGA output voltages for three different
color pixel amplitudes. In this example, the red pixel has the
largest amplitude, and the blue pixel has the smallest amplitude.
Because the PGAOUT_T and PGAOUT_C outputs are inter-
nally buffered by source followers, they are not an exact repre-
sentation of the differential ADC input signal. PGAOUT_T and
PGAOUT_C should only be used during evaluation; perfor-
mance of the AD9816 is only guaranteed with these two pins
unconnected.
–12–
REV. A

12 Page





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