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AD9814 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9814
Beschreibung Complete 14-Bit CCD/CIS Signal Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 15 Seiten
AD9814 Datasheet, Funktion
a
Complete 14-Bit
CCD/CIS Signal Processor
AD9814
FEATURES
14-Bit 10 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel Operation Up to 10 MSPS
1-Channel Operation Up to 7 MSPS
Correlated Double Sampling
1-6x Programmable Gain
؎300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output (8+6 Format)
3-Wire Serial Digital Interface
+3/+5 V Digital I/O Compatibility
28-Lead SOIC Package
Low Power CMOS: 330 mW (Typ)
Power-Down Mode: <1 mW
APPLICATIONS
Flatbed Document Scanners
Film Scanners
Digital Color Copiers
Multifunction Peripherals
PRODUCT DESCRIPTION
The AD9814 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture de-
signed to sample and condition the outputs of trilinear color
CCD arrays. Each channel consists of an input clamp, Corre-
lated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high performance 14-
bit A/D converter.
The CDS amplifiers may be disabled for use with sensors such
as Contact Image Sensors (CIS) and CMOS active pixel sen-
sors, which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal regis-
ters are programmed through a 3-wire serial interface, and pro-
vide adjustment of the gain, offset, and operating mode.
The AD9814 operates from a single +5 V power supply, typi-
cally consumes 330 mW of power, and is packaged in a 28-lead
SOIC.
FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS
CML
CAPT CAPB
AVDD AVSS
DRVDD DRVSS
VINR
VING
VINB
OFFSET
CDS
9-BIT
DAC
CDS
9-BIT
DAC
CDS
9-BIT
DAC
INPUT
CLAMP
BIAS
PGA
AD9814
BANDGAP
REFERENCE
PGA
3:1
MUX
14-BIT
ADC
14 14:8 8
MUX
PGA
6
9
CONFIGURATION
REGISTER
MUX
REGISTER
RED
GREEN
BLUE
RED
GREEN
BLUE
GAIN
REGISTERS
OFFSET
REGISTERS
DIGITAL
CONTROL
INTERFACE
CDSCLK1 CDSCLK2
ADCCLK
OEB
DOUT
SCLK
SLOAD
SDATA
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






AD9814 Datasheet, Funktion
AD9814
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
tAD
tC1
PIXEL N (R, G, B)
tAD
tC2C1
PIXEL (N+1)
tPRA
PIXEL
(N+2)
tADCLK
tC1C2
tADC2
tC2
tC2ADF
tC2ADR tADC1
tADCLK
tOD
R (N–2) G (N–2) G (N–2) B (N–2) B (N–2) R (N–1) R (N–1) G (N–1) G (N–1) B (N–1) B (N–1) R (N)
R (N)
G (N)
G (N)
HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW
BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE BYTE
Figure 1. 3-Channel CDS Mode Timing
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
D<7:0>
tAD
tC1
PIXEL N
tAD
tC1C2
tC2
tC2ADR
PIXEL (N–4)
HIGH BYTE
tADCLK
PIXEL (N–4)
LOW BYTE
tC2C1
tC2ADF
tADCLK
tOD
PIXEL (N–3)
HIGH BYTE
PIXEL (N+1)
tPRB
tADC1
PIXEL (N–3)
LOW BYTE
PIXEL (N–2)
HIGH BYTE
Figure 2. 1-Channel CDS Mode Timing
PIXEL (N+2)
PIXEL (N–2)
LOW BYTE
–6– REV. 0

6 Page









AD9814 pdf, datenblatt
AD9814
CIRCUIT OPERATION
Analog Inputs—CDS Mode
Figure 8 shows the analog input configuration for the CDS
mode of operation. Figure 9 shows the internal timing for the
sampling switches. The CCD reference level is sampled when
CDSCLK1 transitions from high to low, opening S1. The CCD
data level is sampled when CDSCLK2 transitions from high to
low, opening S2. S3 is then closed, generating a differential
output voltage representing the difference between the two sampled
levels.
The input clamp is controlled by CDSCLK1. When CDSCLK1
is high, S4 closes and the internal bias voltage is connected to
the analog input. The bias voltage charges the external 0.1 µF
input capacitor, level-shifting the CCD signal into the AD9814’s
input common-mode range. The time constant of the input
clamp is determined by the internal 5 kresistance and the
external 0.1 µF input capacitance.
CCD SIGNAL
+
1F
VINR
CIN
0.1F
OFFSET
0.1F
AD9814
S1
4pF
CML
5k
S2
AVDD
S4
S3
CML
4pF
1.7k
4V
INPUT CLAMP LEVEL
2.2kIS SELECTED IN THE
3V CONFIGURATION
REGISTER
6.9k
Figure 8. CDS-Mode Input Configuration (All Three Chan-
nels Are Identical)
S1, S4 CLOSED
CDSCLK1
S1, S4 OPEN
S1, S4 CLOSED
CDSCLK2
S2 CLOSED
S2 OPEN
S2 CLOSED
S3 CLOSED
S3 CLOSED
Q3
(INTERNAL)
S3 OPEN
Figure 9. CDS-Mode Internal Switch Timing
External Input Coupling Capacitors
The recommended value for the input coupling capacitors is
0.1 µF. While it is possible to use a smaller capacitor, this larger
value is chosen for several reasons:
1. Signal Attenuation. The input coupling capacitor creates a
capacitive divider with a CMOS integrated circuit’s input
capacitance, attenuating the CCD signal level. CIN should be
large relative to the IC’s 10 pF input capacitance in order to
minimize this effect.
2. Linearity. Some of the input capacitance of a CMOS IC is
junction capacitance, which varies nonlinearly with applied
voltage. If the input coupling capacitor is too small, then the
attenuation of the CCD signal will vary nonlinearly with signal
level. This will degrade the system linearity performance.
3. Sampling Errors. The internal 4 pF sample capacitors have
a “memory” of the previously sampled pixel. There is a
charge redistribution error between CIN and the internal
sample capacitors for larger pixel-to-pixel voltage swings. As
the value of CIN is reduced, the resulting error in the sampled
voltage will increase. With a CIN value of 0.1 µF, the charge
redistribution error will be less than 1 LSB for a full-scale
pixel-to-pixel voltage swing.
Analog Inputs—SHA Mode
Figure 10 shows the analog input configuration for the SHA
mode of operation. Figure 11 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential out-
put voltage representing the difference between the sampled
input voltage and the OFFSET voltage. The input clamp is
disabled during SHA mode operation.
INPUT SIGNAL
VINR
OPTIONAL DC OFFSET
(OR CONNECT TO GND)
OFFSET
VING
AD9814
S1
S2
S3
4pF
CML
4pF RED
CML
GREEN
VINB
BLUE
Figure 10. SHA-Mode Input Configuration (All Three
Channels Are Identical)
CDSCLK2
Q3
(INTERNAL)
S1, S2 CLOSED
S1, S2 OPEN
S3 OPEN
S3 CLOSED
S1, S2 CLOSED
S3 CLOSED
Figure 11. SHA-Mode Internal Switch Timing
–12–
REV. 0

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