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AD9807 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD9807
Beschreibung Complete 12-Bit/10-Bit 6 MSPS CCD/CIS Signal Processors
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 24 Seiten
AD9807 Datasheet, Funktion
a
FEATURES
Pin Compatible 12-Bit and 10-Bit Versions
12-Bit/10-Bit 6 MSPS A/D Converter
Integrated Triple Correlated Double Sampler
3-Channel, 2 MSPS Color Mode
1؋ – 4؋ Analog Programmable Gain Amplifier
Pixel-Rate Digital Gain Adjustment
Pixel-Rate Digital Offset Adjustment
Internal Voltage Reference
No Missing Codes Guaranteed
Microprocessor-Compatible Control Interface
+3.3 V/+5 V Digital I/O Compatibility
Low Power CMOS: 500 mW
64-Pin PQFP Surface Mount Package
Complete 12-Bit/10-Bit 6 MSPS
CCD/CIS Signal Processors
AD9807/AD9805
FUNCTIONAL BLOCK DIAGRAM
PIXEL PIXEL
VREF OFFSET GAIN
AD9807/AD9805
RED
VINR
CDS
PGA
GAIN
REGISTERS
8-10 12-10
REF
GREEN
VING
CDS
PGA
MUX
ADC
12-10
X
DOUT
BLUE
VINB
CDS
PGA
INPUT
OFFSET
CONFIG
REGS
ODD
EVEN
MPU
PMOPRUT
PORT
CDSCLK1 CDSCLK2
ADCCLK
CSB
RD
WR
A2
A1
A0
PRODUCTION DESCRIPTION
The AD9807 and AD9805 are complete CCD/CIS imaging
decoders and signal processors on a single monolithic integrated
circuit. The input of the AD9807/AD9805 allows direct ac
coupling of the charge-coupled device (CCD) or contact image
sensor (CIS) output(s). The AD9807/AD9805 includes all the
circuitry to perform three-channel correlated double sampling
(CDS) and programmable gain adjustment of the CCD output;
a 12-bit or 10-bit analog-to-digital converter (ADC) quantizes
the analog signal. After digitization, the on-board digital signal
processor (DSP) circuitry allows pixel rate offset and gain correc-
tion. The DSP also corrects odd/even CCD register imbalance
errors. A parallel control bus provides a simple interface to
8-bit microcontrollers. The AD9807/AD9805 comes in a
space saving 64-pin plastic quad flatpack (PQFP) and is specified
over the commercial (0°C to +70°C) temperature range. By
disabling the CDS, the AD9807/AD9805 are also suitable for
non-CCD applications, or applications that do not require
CDS, such as CIS signal processing.
PRODUCT HIGHLIGHTS
The AD9807/AD9805 offers a complete, single chip CCD
imaging front end in a 64-pin plastic quad flatpack (PQFP).
On-Chip PGA—The AD9807/AD9805 includes a 3-channel
analog programmable gain amplifier; it is programmable from
1× to 4× in 16 increments.
On-Chip CDS—An integrated 3-channel correlated double
sampler allows easy ac coupling directly from the CCD sensor
outputs. Additionally, the CDS reduces low frequency noise
and reset feedthrough.
On-Chip Voltage Reference—The AD9807/AD9805 includes a
2 V bandgap reference that allows the input range of the device to
be configured for input spans up to 4 V.
6 MSPS A/D Converter—A highly linear 12-bit or 10-bit A/D
converter sequentially digitizes the red, green and blue CDS
outputs ensuring no missing code performance. The user may also
configure the AD9807/AD9805 for single channel operation.
Digital Gain & Offset Correction—Pixel rate digital gain and
offset correction blocks allow precise repeatable correction of
imaging system error sources.
Digital I/O Compatibility—The AD9807/AD9805 offers
+3.3 V/+5 V logic level compatibility.
Pin-Compatible 12-Bit and 10-Bit Versions—The AD9807 is
also offered in a pin-compatible 10-bit version, the AD9805,
allowing upgrade-ability and simplifying design issues across
different scanner models.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997






AD9807 Datasheet, Funktion
AD9807/AD9805
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
AVDD 1
AVSS 2
CAPT 3
CAPT 4
CAPB 5
CAPB 6
VREF 7
CML 8
VINR 9
AVSS 10
VING 11
AVSS 12
VINB 13
AVSS 14
AVDD 15
STRTLN 16
PIN 1
IDENTIFIER
AD9805
TOP VIEW
(Not to Scale)
48 A0
47 DOUT<9>
46 DOUT<8>
45 DOUT<7>
44 DOUT<6>
43 DOUT<5>/MPU<7>
42 DOUT<4>/MPU<6>
41 DRVDD
40 DRVSS
39 DOUT<3>/MPU<5>
38 DOUT<2>/MPU<4>
37 DOUT<1>/MPU<3>
36 DOUT<0>/MPU<2>
35 MPU<1>
34 MPU<0>
33 OEB
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
PIN DESCRIPTIONS
Pin No.
Pin Name
Type
Description
1, 15
2, 10, 12, 14
3, 4
5, 6
7
8
9
11
13
16
17
18
19
28, 52
29, 51
20
21–26
27
30
31
32
33
34
35
36
37–39, 42
40
41
43
44–46
47
48, 49, 50
53, 54
55
56–63
64
AVDD
AVSS
CAPT
CAPB
VREF
CML
VINR
VING
VINB
STRTLN
CDSCLK1
CDSCLK2
ADCCLK
DVSS
DVDD
OFFSET<7>
OFFSET<6:1>
OFFSET<0>
CSB
RDB
WRB
OEB
MPU<0>
MPU<1>
DOUT<0>/MPU<2>
DOUT<1:4>/MPU<3:6>
DRVSS
DRVDD
DOUT<5>/MPU<7>
DOUT<6:8>
DOUT<9>
A0, A1, A2
NC
GAIN<0>
GAIN<1:8>
GAIN<9>
P
P
AO
AO
AO
AO
AI
AI
AI
DI
DI
DI
DI
P
P
DI
DI
DI
DI
DI
DI
DI
DIO
DIO
DIO
DIO
P
P
DIO
DO
DO
DI
DI
DI
DI
+5 V Analog Supply.
Analog Ground.
Reference Decoupling. See Figure 22.
Reference Decoupling.
Internal Reference Output. Decouple with 10 µF + 0.1 µF.
Internal Bias Voltage. Decouple with 0.1 µF.
Analog Input, Red.
Analog Input, Green.
Analog Input, Blue.
STRTLN. Indicates beginning of scan line.
CDS Reset Clock Pulse Input.
CDS Data Clock Pulse Input.
A/D Sample Clock Input.
Digital Ground.
+5 V Digital Supply.
Pixel Rate Offset Coefficient Inputs. Most Significant Bit.
Pixel Rate Offset Coefficient Inputs.
Pixel Rate Offset Coefficient Inputs. Least Significant Bit.
Chip Select. Active Low.
Read Strobe. Active Low.
Write Strobe. Active Low.
Output Enable. Active Low.
Register Input-Output LSB.
Register Input-Output.
Data Output LSB/Register Input-Output.
Data Output/Register Input-Output.
Digital Driver Ground.
Digital Driver Supply.
Data Output/Register Input-Output MSB.
Data Outputs.
Data Output MSB.
Register Select Pins.
No Connection.
Pixel Rate Gain Coefficient Input LSB.
Pixel Rate Gain Coefficient Inputs.
Pixel Rate Gain Coefficient Input MSB.
TYPE: AI = Analog Input; AO = Analog Output; DI = Digital Input; DO = Digital Output; DIO = Digital Input/Output; P = Power.
–6– REV. 0

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AD9807 pdf, datenblatt
AD9807/AD9805
Color Pointer
Both the AD9807 and the AD9805 use Bits 6 and 7 in the
Configuration Register to direct data to the corresponding
internal registers. Table III shows the mapping of Bits 6 and 7
to their corresponding color.
Table III. Color Pointer Map
Bit 7
Bit 6
Color Register
0 0 Red
0 1 Green
1 0 Blue
1 1 RESERVED
Configuration Register 2
Configuration Register 2 controls several functions: color/black
and white selection, CDS enabling, A/D Reference Control
and Input Clamp Mode. Figure 7 shows the AD9807 and
AD9805 Configuration Register 2 format. Setting Bit 0 enables
the three internal CDS blocks of the AD9807/AD9805. Reset-
ting Bit 0 disables the internal CDS blocks, configuring the part
for SHA operation. Setting Bit 1 places the AD9807/AD9805 in
single-channel (black & white) mode. In this mode, only one of
the three input channels is used. The color bits in the configu-
ration register at the time of the last write indicate the particular
channel used. Resetting Bit 1 places the AD9807/AD9805 in
color mode and all three input channels are enabled. Bits 2-4
control the full-scale input span of the A/D. Setting Bit 2 results in
a 4 V p-p input span. Setting Bit 3 results in a 2 V p-p full-scale
input span. Setting Bit 4 results in a full-scale span set by an
external reference connected to the VREF pin of the AD9807/
AD9805 (Full Scale = 2 × VREF). Resetting Bits 2, 3 or 4
disables that particular mode. Bits 6 and 7 select the desired
clamp mode (see Figure 17). Table IV shows the truth table
for clamp mode functionality. Line clamp mode allows control
of the input switch (S1) via CDSCLK1 only while STRTLN is
reset. Pixel clamp mode allows control of the input switch (S1)
via CDSCLK1 regardless of the state of STRTLN. No clamp
mode disables the input switch (S1) regardless of the selected
mode of CDS operation.
Table IV. Clamp Mode Truth Table
Bit 7
Bit 6
Clamp Mode
0 0 Line Clamp
0 1 Pixel Clamp
1 0 No Clamp
1 1 RESERVED
76 54 3 21 0
Input Offset Registers
The Input Offset Registers control the amount of analog offset
applied to the analog inputs prior to the PGA portion of the
AD9807/AD9805; there is one Input Offset Register for each
color. Figure 8 shows the Input Offset Register format. The
offset range may be varied between –80 mV and 20 mV. The
data format for the Input Offset Registers is straight binary
coding. An all “zeros” data word corresponds to –80 mV. An
all “ones” data word corresponds to 20 mV. The offset is
variable in 256 steps. The contents of the color pointer in the
Configuration Register at the time an Input Offset Register is
written indicates the color for which that offset setting applies.
76 54 3 21 0
ANALOG OFFSET (LSB)
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET
ANALOG OFFSET (MSB)
Figure 8. Input Offset Registers Format
PGA Gain Registers
Bits 0–3 of the PGA Gain Registers control the amount of gain
applied to the analog inputs prior to the A/D conversion
portion of the AD9807/AD9805; there is one PGA Gain
Register for each channel. Figure 9 shows the PGA Gain Register
format. The gain range may be varied between 1 and 4. The
data format for the PGA Gain Registers is straight binary
coding. An all “zeros” data word corresponds to an analog
gain of 1. An all “ones” data word corresponds to an analog
gain of 4. The gain is variable in 16 steps (see Figure 16).
The contents of the color pointer in the Configuration
Register at the time a PGA Gain Register is written indicates
the color for which that gain setting applies. Bits 4–7 of the PGA
Gain Registers are reserved.
76 54 3 21 0
PGA0
PGA1
PGA2
PGA3
RESERVED
RESERVED
RESERVED
RESERVED
CDSEN
BLACK & WHITE
ADC FULL SCALE = 4V
ADC FULL SCALE = 2V
EXTERNAL REFERENCE
SET TO 0
CLAMP MODE SELECT
CLAMP MODE SELECT
Figure 7. AD9807/AD9805 Configuration Register 2 Format
Figure 9. PGA Gain Registers Format
Odd, Even Offset Registers
The Odd and Even Offset Registers provide a means of digitally
compensating the odd and even offset error (Register Imbal-
ance) typical of multiplexed CCD imagers; there is one Odd
and one Even Offset Register for each color. Figure 10 shows
the AD9807/AD9805 Odd and Even Offset Register Formats.
The data format for the Odd and Even Offset Registers is twos
complement. The offsets may be varied between positive
–12–
REV. 0

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