PDF AD9806 Data sheet ( Hoja de datos )

Número de pieza	AD9806
Descripción	Complete 10-Bit 18 MSPS CCD Signal Processor
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES Pin-Compatible with Industry Standard AD9803 18 MSPS Correlated Double Sampler (CDS) Low Noise PGA with 0 dB to 34 dB Gain Range Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 18 MSPS A/D Converter AUX Input with Input Clamp and PGA Direct ADC Input with Input Clamp AUXMID Input with PGA 3-Wire Serial Interface for Digital Control Two Auxiliary 8-Bit DACs 3 V Single Supply Operation Low Power: 65 mW @ 2.7 V Supply 48-Lead LQFP Package APPLICATIONS Camcorders (8 mm and DVC) Digital Still Cameras Complete 10-Bit 18 MSPS CCD Signal Processor AD9806 PRODUCT DESCRIPTION The AD9806 is a complete analog signal processor for CCD applications. It features an 18 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9806’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally programmable gain amplifier (PGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjust- ment, black level adjustment, input configuration, and power- down modes. The AD9806 operates from a single 3 V power supply, typically dissipating 75 mW. Packaged in a space-saving 48-lead LQFP, the AD9806 is specified over an operating temperature range of –20°C to +85 C. CCDIN CLPDM DAC1 DAC2 FUNCTIONAL BLOCK DIAGRAM PBLK CLPOB CDS CLAMP 0dB~34dB PGA MUX S/H AD9806 10 ADC DOUT CLAMP 8-BIT DAC 8-BIT DAC 10-BIT DAC INTF 3 0dB~15dB –4~14dB PGA PGA REF CLAMP TIMING GENERATOR VRT VRB 3-W INTF ADCIN AUXIN AUXMID SHP SHD ADCCLK REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 1 page ADC-MODE SPECIFICATIONS (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Parameter Min Typ Max POWER CONSUMPTION (Same as AUX-MODE) MAXIMUM CLOCK RATE (Same as AUX-MODE) ACTIVE CLAMP (Same as AUX-MODE) TIMING SPECIFICATIONS1 (Same as AUX-MODE) Specifications subject to change without notice. DAC SPECIFICATIONS (DAC1 and DAC2) Parameter RESOLUTION MIN OUTPUT MAX OUTPUT MAX CURRENT LOAD MAX CAPACITIVE LOAD Specifications subject to change without notice. Min Typ 8 0.1 VDD – 0.1 1 500 Max ABSOLUTE MAXIMUM RATINGS Parameter With Respect To Min Max AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL CCDIN, CLPOUT, CLPREF, CLPBYP Junction Temperature Lead Temperature (10 sec) AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS –0.3 +3.9 –0.3 +3.9 –0.3 +3.9 –0.3 DRVDD + 0.3 –0.3 DVDD + 0.3 –0.3 DVDD + 0.3 –0.3 DVDD + 0.3 –0.3 AVDD + 0.3 –0.3 AVDD + 0.3 150 300 AD9806 Unit Unit Bits V V mA pF Unit V V V V V V V V V °C °C Model AD9806KST Temperature Range –20°C to +85°C ORDERING GUIDE Package Description Thin Plastic Quad Flatpack (LQFP) Package Option ST-48 THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9806 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– 5 Page AD9806 APPLICATION INFORMATION Grounding and Decoupling Recommendations As shown in Figure 10, a single ground plane is recommended for the AD9806. This ground plane should be as continuous as possible, particularly around Pins 25 through 37. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9806, but a separate digital driver supply may be used for DRVDD (Pin 12). DRVDD should always be decoupled to DRVSS (Pin 13), which should be connected to the analog ground plane. The advantages of using a separate digital driver supply include using a lower volt- age (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. Using the AD9806 in AD9803 Sockets The AD9806 may be easily used in existing AD9803 designs without any circuit modifications. Most of the pin assignments are the same for both ICs. Table I outlines the differences. The circuit of Figure 10 shows the necessary connections for the AD9806 when used in an existing AD9803 socket. If the two auxiliary DACs are not used, then Pins 39 and 40 (DAC1 and DAC2) may be grounded. If the AUX or ADC modes are needed, then the input signal should be connected to either AUXIN or ADCIN through a 0.1 µF capacitor, in the same way that CCDIN is used with the input signal. Table I. AD9806/AD9803 Pin Differences Pin No. AD9803 AD9806 Circuit Connection 1 NC 15 ACLP 24 NC 25 CCDBYP2 27 PIN 28 CCDBYP2 29 PGABYP1 30 PGABYP2 35 AUXCONT 38 VTRBYP NC NC NC CLPOUT NC CLPREF NC NC AUXMID NC Ground Ground Ground Decoupled with 0.1 µF to Ground Shorted to Pin 26 Decoupled with 0.1 µF to Ground Decoupled with 0.1 µF to Ground Shorted to Pin 29 Ground, or decoupled with 0.1 µF to Ground Decoupled with 0.1 µF to Ground Using the AD9806 in New Designs Figure 11 shows the recommended circuit for using the AD9806 in new designs. Three external decoupling capacitors have been removed from the circuit shown in Figure 9, one from Pin 29, one from Pin 38, and one from between Pins 47 and 48. Note that the decoupling capacitors for Pins 47 (VRB) and 48 (VRT) must be increased to 1.0 µF when used in this configuration. 0.1␮F 0.1␮F 1.0␮F VDD 0.1␮F SDATA SCK SL 0.1␮F 0.1␮F VOUT2 VOUT1 48 47 46 45 44 43 42 41 40 39 38 37 DIGITAL OUTPUT DATA 1 NC 2 D0 (LSB) 3 D1 4 D2 5 D3 6 D4 7 D5 8 D6 9 D7 10 D8 11 D9 (MSB) 12 DRVDD AD9806 ADCIN 36 AUXMID 35 AUXIN 34 ACVDD 33 CLPBYP 32 ACVSS 31 NC 30 NC 29 CLPREF 28 NC 27 DIN 26 CLPOUT 25 0.1␮F 0.1␮F 0.1␮F 0.1␮F VDD 0.1␮F CCD SIGNAL INPUT VDD 13 14 15 16 17 18 19 20 21 22 23 24 0.1␮F VDD 0.1␮F NC = NO CONNECT 0.1␮F CLPDM SHD SHP CLPOB PBLK ADCCLK Figure 10. CCD-Mode Circuit Configuration Used in AD9803 Socket REV. 0 –11– 11 Page

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