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PDF AD9803 Data sheet ( Hoja de datos )
| Número de pieza | AD9803 | |
| Descripción | CCD Signal Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
3-Wire Serial I/F for Digital Control
18 MHz Correlated Double Sampler
Low Noise PGA with 0 dB–30 dB Range
Analog Pre-Blanking Function
AUX Input with Input Clamp and PGA
10-Bit 18 MSPS A/D Converter
Direct ADC Input with Input Clamp
Internal Voltage Reference
Two Auxiliary 8-Bit DACs
+3 V Single Supply Operation
Low Power: 150 mW at 2.7 V Supply
48-Lead LQFP Package
CCD Signal Processor
for Electronic Cameras
AD9803
PRODUCT DESCRIPTION
The AD9803 is a complete CCD and video signal processor
developed for electronic cameras. It is well suited for video
camera and still-camera applications.
The 18 MHz CCD signal processing chain consists of a CDS,
low noise PGA, and 10-bit ADC. Required clamping circuitry
and a voltage reference are also provided. The AUX input
features a wideband PGA and input clamp, and can be used to
sample analog video signals.
The AD9803 nominally operates from a single 3 V power sup-
ply, typically dissipating 170 mW. The AD9803 is packaged in a
space-saving 48-lead LQFP and is specified over an operating
temperature range of –20°C to +70°C.
CCDIN
CLPDM
DAC1
DAC2
FUNCTIONAL BLOCK DIAGRAM
PBLK
PGACONT1-2 CLPOB
CDS
CLAMP
0–30dB
PGA
MUX S/H
AD9803
10
ADC
DOUT
CLAMP
8-BIT
DAC
8-BIT
DAC
10-BIT
DAC
INTF
3
0–10dB
PGA
CLAMP
REF
TIMING
GENERATOR
AUXCONT
VRT
VRB
3-W INTF ADCIN AUXIN ACLP SHP SHD ADCCLK
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
TIMING SPECIFICATIONS
AD9803
CCD
N
N+1 N+2 N+3 N+4
SHP
SHD
tINHIBIT
tID
tID
ADCCLK
D0–D9
tOD
N–8
tHOLD
N–7
ADCCLK RISING EDGE PLACEMENT
N–6 N–5 N–4
N–3
NOTES:
1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES.
2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (tINHIBIT).
3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP.
4. OUTPUT LATENCY (7 CYCLES) SHOWN WITH EVEN-ODD OFFSET CORRECTION ENABLED.
5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN.
Figure 1. CCD-MODE Timing
VIDEO
INPUT
ADCCLK
D0–D9
N N+1
tOD
tHOLD
N–4
N+2
tID
N+3
N–3 N–2
N+4
N–1
NOTE:
EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE.
Figure 2. AUX-MODE and ADC-MODE Timing
N+5
N
CCD
SIGNAL
EFFECTIVE
PIXELS
OPTICAL BLACK
BLANKING
INTERVAL
DUMMY BLACK
EFFECTIVE
PIXELS
CLPOB
CLPDM
PBLK
NOTES:
1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED.
2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE.
3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p.
4. CLPDM OVERWRITES PBLK.
5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN.
Figure 3. CCD-MODE Clamp Timing
REV. 0
–5–
5 Page 
THEORY OF OPERATION
Introduction
The AD9803 is a 10-bit analog-to-digital interface for CCD
cameras. The block level diagram of the system is shown in
Figure 23. The device includes a correlated double sampler
(CDS), 0 dB–30 dB programmable gain amplifier (PGA), black
level correction loop, input clamp and voltage reference. The
only external analog circuitry required at the system level is an
emitter follower buffer between the CCD output and AD9803
inputs.
CLPDM
INPUT CLAMP
DIFFERENTIAL SIGNAL PATH
PIN
CDS
PGA
SHA
DIN
ADC
INTEG
BLACK LEVEL CLAMP
CLPOB
Figure 23. CCD Mode Signal Path
Correlated Double Sampling (CDS)
CDS is important in high performance CCD systems as a
method for removing several types of noise. Basically, two
samples of the CCD output are taken: one with the signal
present (“data”) and one without (“reference”). Subtracting
these two samples removes any noise which is common—or
correlated—to both.
Figure 24 shows the block diagram of the AD9803’s CDS. The
S/H blocks are directly driven by the input and the sampling
function is performed passively, without the use of amplifiers.
This implementation relies on the off-chip emitter follower
buffer to drive the two 10 pF sampling capacitors. Only one
capacitor at a time is seen at the input pin.
FROM
CCD
S/H
S OUT
Q1
S/H
Q2
10pF
Figure 24. CDS Block Diagram
The AD9803 actually uses two CDS circuits in a “ping pong”
fashion to allow the system more acquisition time. In this way,
the output from one of the two CDS blocks will be valid for an
entire clock cycle. Thus, the bandwidth requirement of the
subsequent gain stage is reduced as compared to that for a single-
channel CDS system. This lower bandwidth translates to lower
power and noise.
AD9803
Programmable Gain Amplifier (PGA)
The on-chip PGA provides a gain range of 0 dB–30 dB, which
is “linear in dB.” Typical gain characteristics are shown in
Figures 25 and 26.
40
35
30
25
20
15
10
5
0
–5
0 0.5 1.0 1.5 2.0 2.5 3.0
PGACONT1 – Volts
Figure 25. PGA Gain Curve—Analog Control
40
35
30
25
20
15
10
5
0
–5
0 171 341 511 682 852 1023
PGA GAIN REGISTER
Figure 26. PGA Gain Curve—Digital Control
As shown in Figure 27, analog PGA control is provided through
the PGACONT1 and PGACONT2 inputs. PGACONT1 pro-
vides coarse and PGACONT2 fine (1/16) gain control. The
PGA gain can also be controlled using the internal 10-bit DAC
through the serial digital interface. The gain characteristic
shown in Figure 26, with the internal DAC providing the same
control range as PGACONT1. See the Serial Interface Specifi-
cations for more details.
PGACONT1 PGACONT2
A
PGACONT1 = COARSE CONTROL
PGACONT2 = FINE (1/16) CONTROL
Figure 27. Analog PGA Control
REV. 0
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11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AD9803.PDF ] | |
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