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PDF AD977A Data sheet ( Hoja de datos )
| Número de pieza | AD977A | |
| Descripción | 16-Bit/ 100 kSPS/200 kSPS BiCMOS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Fast 16-Bit ADC
100 kSPS Throughput Rate—AD977
200 kSPS Throughput Rate—AD977A
Single 5 V Supply Operation
Power Dissipation 100 mW Max
Power-Down Mode 50 W
Input Ranges:
Unipolar; 0 V–10 V, 0 V–5 V and 0 V–4 V
Bipolar; ؎10 V, ؎5 V and ؎3.3 V
Choice of External or Internal 2.5 V Reference
High Speed Serial Interface
On-Chip Clock
20-Lead Skinny DIP or SOIC Package
28-Lead Skinny SSOP Package
16-Bit, 100 kSPS/200 kSPS
BiCMOS A/D Converter
AD977/AD977A
FUNCTIONAL BLOCK DIAGRAM
REF
VANA AGND1
CAP
R1IN
R2IN
R3IN
4R
2R
R
4k⍀
2.5V
REFERENCE
AD977/
AD977A
SERIAL
4R
SWITCHED
DATA
CAP ADC
INTERFACE
AGND2
VDIG
R = 5k⍀ AD977
R = 2.5k⍀ AD977A
CONTROL LOGIC &
INTERNAL CALIBRATION CIRCUITRY
CLOCK
SYNC
BUSY
DATACLK
DATA
DGND PWRD R/C CS TAG SB/BTC EXT/INT
GENERAL DESCRIPTION
The AD977/AD977A is a high speed, low power 16-bit A/D
converter that operates from a single 5 V supply. The AD977A
has a throughput rate of 200 kSPS whereas the AD977 has a
throughput rate of 100 kSPS. Each part contains a successive
approximation, switched capacitor ADC, an internal 2.5 V
reference, and a high speed serial interface. The ADC is factory
calibrated to minimize all linearity errors. The AD977/AD977A is
specified for full scale bipolar input ranges of ± 10 V, ± 5 V and
±3.3 V, and unipolar ranges of 0 V to 10 V, 0 V to 5 V and
0 V to 4 V.
The AD977/AD977A is comprehensively tested for ac param-
eters such as SNR and THD, as well as the more traditional dc
parameters of offset, gain and linearity.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD977/AD977A is a high speed, 16-bit ADC based on
a factory calibrated switched capacitor architecture.
2. Single-Supply Operation
The AD977/AD977A operates from a single 5 V supply and
dissipates only 100 mW max.
3. Comprehensive DC and AC Specifications
In addition to the traditional specifications of offset, gain
and linearity, the AD977/AD977A is fully tested for SNR
and THD.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD977/AD977A
ABSOLUTE MAXIMUM RATINGS1
Analog Inputs
R1IN, R2IN , R3IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 V
CAP . . . . . . . . . . . . . . . . .+VANA + 0.3 V to AGND2 – 0.3 V
REF . . . . . . . . . . . . . . . . . . . . . Indefinite Short to AGND2,
. . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VANA
Ground Voltage Differences
DGND, AGND1, AGND2 . . . . . . . . . . . . . . . . . . . ± 0.3 V
Supply Voltages
VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDIG to VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V
VDIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Digital Inputs . . . . . . . . . . . . . . . . . . . –0.3 V to VDIG + 0.3 V
Internal Power Dissipation2
PDIP (N), SOIC (R), SSOP (RS) . . . . . . . . . . . . . 700 mW
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range N, R . . . . . . . . –65°C to +150°C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Specification is for device in free air:
20-Lead PDIP: θJA = 100°C/W, θJC = 31°C/W,
20-Lead SOIC: θJA = 75°C/W, θJC = 24°C/W,
28-Lead SSOP: θJA = 109°C/W, θJC = 39°C/W.
PIN CONFIGURATIONS
SOIC and DIP
SSOP
R1IN 1
20 VDIG
AGND1 2
19 VANA
R2IN 3
18 PWRD
R3IN 4
CAP 5
AD977 17 BUSY
AD977A 16 CS
REF
6
TOP VIEW
(Not to Scale)
15
R/C
AGND2 7
14 TAG
SB/BTC 8
13 DATA
EXT/INT 9
12 DATACLK
DGND 10
11 SYNC
R1IN 1
AGND1 2
28 VDIG
27 VANA
R2IN 3
26 PWRD
R3IN 4
25 BUSY
NC 5
24 CS
CAP 6 AD977 23 NC
REF 7 AD977A 22 NC
NC
8
TOP VIEW
(Not to Scale)
21
R/C
AGND2 9
20 NC
NC 10
19 TAG
NC 11
18 NC
SB/BTC 12
17 DATA
EXT/INT 13
16 DATACLK
DGND 14
15 SYNC
NC = NO CONNECT
1.6mA IOL
TO OUTPUT
PIN
CL
100pF
500A
IOH
1.4V
Figure 1. Load Circuit for Digital Interface Timing
ORDERING GUIDE
Model
Temperature
Range
Throughput
Rate
AD977AN
AD977BN
AD977CN
AD977AAN
AD977ABN
AD977ACN
AD977AR
AD977BR
AD977CR
AD977AAR
AD977ABR
AD977ACR
AD977ARS
AD977BRS
AD977CRS
AD977AARS
AD977ABRS
AD977ACRS
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
100 kSPS
100 kSPS
100 kSPS
200 kSPS
200 kSPS
200 kSPS
100 kSPS
100 kSPS
100 kSPS
200 kSPS
200 kSPS
200 kSPS
100 kSPS
100 kSPS
100 kSPS
200 kSPS
200 kSPS
200 kSPS
*N = 20-lead 300 mil plastic DIP; R = 20-lead SOIC; RS = 28-lead SSOP.
Max INL
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
± 2.0 LSB
± 3.0 LSB
± 2.0 LSB
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD977/AD977A feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Min S/(N+D)
83 dB
85 dB
83 dB
83 dB
85 dB
83 dB
83 dB
85 dB
83 dB
83 dB
85 dB
83 dB
83 dB
85 dB
83 dB
83 dB
85 dB
83 dB
Package
Options*
N-20
N-20
N-20
N-20
N-20
N-20
R-20
R-20
R-20
R-20
R-20
R-20
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
WARNING!
ESD SENSITIVE DEVICE
REV. D
–5–
5 Page 
EXT
DATACLK
R/C
BUSY
SYNC
DATA
TAG
0
t15 t15
t2
t12
t13 t14
1 234
t15
t17
t12
t18
t23
t24
TAG 0
BIT 15
(MSB)
TAG 1
BIT 14
TAG 2
AD977/AD977A
17 18
t18
BIT 0
(LSB)
TAG 0
TAG 1
TAG 2
TAG 16 TAG 17 TAG 18 TAG 19
Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set
to Logic Low)
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either CS is High or while both CS and R/C
are low. In Figure 7 a conversion is initiated by taking R/C low
with CS tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/C is taken low the BUSY
output will go low to indicate that the conversion process has
began. Figure 7 shows R/C then going high and after a delay of
greater than 15 ns (t15) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear
approximately 40 ns after this rising edge and will be valid on
the falling edge of clock pulse #1 and the rising edge of clock
pulse #2. The MSB will be valid approximately 40 ns after the
rising edge of clock pulse #2 and can be latched off either the
falling edge of clock pulse #2 or the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18, the DATA output
pin will reflect the state of the TAG input pin during the
rising edge of clock pulse #2.
EXT
DATACLK
R/C
t15
0
t1
BUSY
SYNC
t2
DATA
t12
t13 t14
1
t15
2
3
t20
t17
t12
t18
BIT 15
(MSB)
BIT 14
18
t22
t18
BIT 0
(LSB)
TAG 0
Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External
Discontinuous Data Clock (EXT/ INT Set to Logic High, CS Set to Logic Low)
REV. D
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD977A.PDF ] | |
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