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PDF AD9773 Data sheet ( Hoja de datos )
| Número de pieza | AD9773 | |
| Descripción | Dual TxDAC D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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12-Bit, 160 MSPS, 2×/4×/8× Interpolating
Dual TxDAC D/A Converter
AD9773
FEATURES
12-bit resolution, 160 MSPS/400 MSPS
input/output data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/2, fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI port
Excellent ac performance
SFDR −69 dBc @ 2 MHz to 35 MHz
WCDMA ACPR −69 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or
TTL/CMOS/LVPECL compatible
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: typical 1.2 W @ 3.3 V
On-chip 1.2 V reference
80-lead thin quad flat package, exposed pad (TQFP_EP)
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
AD9773
12
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
12
DATA
ASSEMBLER
HALF-
BAND
FILTER1*
I 16
LATCH
16
HALF- HALF-
BAND
BAND
FILTER2* FILTER3*
16 16
Q 16
LATCH
16
16 16
COS
SIN
fDAC/2, 4, 8
SIN
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
WRITE
SELECT
MUX
CONTROL
CLOCK OUT
/2
SPI INTERFACE AND
CONTROL REGISTERS
/2
/2
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
FILTER
BYPASS
MUX
/2
COS
(fDAC)
PRESCALER
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
Figure 1.
IDAC
GAIN
DAC
OFFSET
DAC
I/Q DAC
GAIN/OFFSET
REGISTERS
IDAC
IOUT
DIFFERENTIAL
CLK
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9773
GENERAL DESCRIPTION
The AD97731 is the 12-bit member of the AD977x pin-
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+® family. The AD977x family features
a serial port interface (SPI) that provides a high level of
programmability, thus allowing for enhanced system-level
options. These options include selectable 2×/4×/8× interpo-
lation filters; fS/2, fS/4, or fS/8 digital quadrature modulation
with image rejection; a direct IF mode; programmable channel
gain and offset control; programmable internal clock divider;
straight binary or twos complement data interface; and a single-
port or dual-port data interface.
The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simultaneously
enhancing the TxDAC+ family’s pass-band noise/distortion
performance. The independent channel gain and offset adjust
registers allow the user to calibrate LO feedthrough and side-
band suppression errors associated with analog quadrature
modulators. The 6 dB of gain adjustment range can also be
used to control the output power level of each DAC.
The AD9773 features the ability to perform fS/2, fS/4, and fS/8
digital modulation and image rejection when combined with an
analog quadrature modulator. In this mode, the AD9773
accepts I and Q complex data (representing a single or multi-
carrier waveform), generates a quadrature modulated IF signal
along with its orthogonal representation via its dual DACs, and
presents these two reconstructed orthogonal IF carriers to an
analog quadrature modulator to complete the image rejection
upconversion process. Another digital modulation mode (for
example, the direct IF mode) allows the original baseband
signal representation to be frequency translated such that pairs
of images fall at multiples of one-half the DAC update rate.
The AD977x family includes a flexible clock interface accepting
differential or single-ended sine wave or digital logic inputs.
An internal PLL clock multiplier is included and generates the
necessary on-chip high frequency clocks. It can also be disabled
to allow the use of a higher performance external clock source.
An internal programmable divider simplifies clock generation
in the converter when using an external clock source. A flexible
data input interface allows for straight binary or twos complement
formats and supports single-port interleaved or dual-port data.
1 Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other
patents pending.
Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range. The
AD9773 is manufactured on an advanced 0.35 micron CMOS
process, operates from a single supply of 3.1 V to 3.5 V, and
consumes 1.2 W of power.
Targeted at a wide dynamic range, multicarrier, and multi-
standard systems, the superb baseband performance of the
AD9773 is ideal for wide band CDMA, multicarrier CDMA,
multicarrier TDMA, multicarrier GSM, and high performance
systems employing high order QAM modulation schemes. The
image rejection feature simplifies and can help to reduce the
number of signal band filters needed in a transmit signal chain.
The direct IF mode helps to eliminate a costly mixer stage for a
variety of communications systems.
PRODUCT HIGHLIGHTS
1. The AD9773 is the 12-bit member of the AD977x pin
compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family.
2. Direct IF transmission is possible for 70 MHz + IFs
through a novel digital mixing process.
3. fS/2, fS/4, and fS/8 digital quadrature modulation and user
selectable image rejection simplify/remove cascaded SAW
filter stages.
4. A 2×/4×/8× user selectable interpolating filter eases data
rate and output signal reconstruction filter requirements.
5. User selectable twos complement/straight binary
data coding.
6. User programmable channel gain control over 1 dB range
in 0.01 dB increments.
7. User programmable channel offset control ±10% over
the FSR.
8. Ultrahigh speed 400 MSPS DAC conversion rate.
9. Internal clock divider provides data rate clock for
easy interfacing.
10. Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.
11. Low power: Complete CMOS DAC operates on 1.2 W from a
3.1 V to 3.5 V single supply. The 20 mA full-scale current can
be reduced for lower power operation, and several sleep
functions reduce power during idle periods.
12. On-chip voltage reference: The AD9773 includes a 1.20 V
temperature compensated band gap voltage reference.
13. 80-lead thin quad flat package, exposed pad (TQFP_EP).
Rev. D | Page 4 of 60
5 Page 
AD9773
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CLKVDD 1
LPF 2
CLKVDD 3
CLKGND 4
CLK+ 5
CLK– 6
CLKGND 7
DATACLK/PLL_LOCK 8
DGND 9
DVDD 10
P1B11 (MSB) 11
P1B10 12
P1B9 13
P1B8 14
P1B7 15
P1B6 16
DGND 17
DVDD 18
P1B5 19
P1B4 20
PIN 1
AD9773
TxDAC+
TOP VIEW
(Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC = NO CONNECT
60 FSADJ1
59 FSADJ2
58 REFIO
57 RESET
56 SPI_CSB
55 SPI_CLK
54 SPI_SDIO
53 SPI_SDO
52 DGND
51 DVDD
50 NC
49 NC
48 NC
47 NC
46 P2B0 (LSB)
45 P2B1
44 DGND
43 DVDD
42 P2B2
41 P2B3
Figure 5. Pin Configuration
Rev. D | Page 10 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9773.PDF ] | |
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