PDF AS7C31026-20JC Data sheet ( Hoja de datos )

Número de pieza	AS7C31026-20JC
Descripción	5V/3.3V 64K16 CMOS SRAM
Fabricantes	ETC
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No Preview Available ! May 2000 AS7C1026 AS7C31026 ® 5V/3.3V 64K×16 CMOS SRAM Features • AS7C1026 (5V version) • AS7C31026 (3.3V version) • Industrial and commercial versions • Organization: 65,536 words x 16 bits • Center power and ground pins for low noise • High speed - 10/12/15/20 ns address access time - 5/6/8/10 ns output enable access time • Low power consumption: ACTIVE - 880 mW (AS7C1026) / max @ 12 ns - 396 mW (AS7C31026) / max @ 12 ns • Low power consumption: STANDBY - 28 mW (AS7C1026) / max CMOS I/O - 18 mW (AS7C31026) / max CMOS I/O • 2.0V data retention • Easy memory expansion with CE, OE inputs • TTL-compatible, three-state I/O • JEDEC standard packaging - 44-pin 400 mil SOJ - 44-pin 400 mil TSOP II - 48-ball 6 mm × 8 mm CSP mBGA • ESD protection ≥ 2000 volts • Latch-up current ≥ 200 mA Logic block diagram A0 A1 A2 A3 A4 A5 A6 A7 I/O0–I/O7 I/O8–I/O15 I/O buffer WE UB OE LB CE 64K × 16 Array Control circuit Column decoder Pin arrangement 44-Pin SOJ, TSOP II (400 mil) VCC A4 GND A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC GND I/O4 I/O5 I/O6 I/O7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 A5 43 A6 42 A7 48-CSP mini Ball-Grid-Array Package 41 OE 40 UB 1 2 3 45 6 39 LB 38 37 I/O15 A I/O14 LB OE A0 A1 A2 NC 36 I/O13 B I/O8 UB A3 A4 CE I/O0 35 34 I/O12 GND C I/O9 I/O10 A5 A6 I/O1 I/O2 33 32 VCC I/O11 D VSS I/O11 NC A7 I/O3 VDD 31 30 I/O10 I/O9 E VDD I/O12 NC NC I/O4 VSS 29 28 I/O8 NC F I/O14 I/O13 A14 A15 I/O5 I/O6 27 A8 26 A9 G I/O15 NC A12 A13 WE I/O7 25 24 A10 A11 H NC A8 A9 A10 A11 NC 23 NC Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current Shaded areas indicate preliminary information. AS7C1026 AS7C31026 AS7C1026 AS7C31026 AS7C1026-12 AS7C1026-15 AS7C1026-20 AS7C31026-10 AS7C31026-12 AS7C31026-15 AS7C31026-20 10 12 15 20 5 6 8 10 – 160 150 140 125 110 100 90 –333 3333 Unit ns ns mA mA mA mA DID 11-20011-A. 5/22/00 ALLIANCE SEMICONDUCTOR 1 Copyright ©1999 Alliance Semiconductor. All rights reserved. 1 page AS7C1026 AS7C31026 ® Write cycle (over the operating range) -10 -12 -15 -20 Parameter Symbol Min Max Min Max Min Max Min Max Unit Write cycle time Chip enable (CE) to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Byte select low to end of write Shaded areas indicate preliminary information. tWC 10 – 12 – 15 – 20 – tCW 8 – 8 – 12 – 13 – tAW 8 – 9 – 10 – 12 – tAS 0 – 0 – 0 – 0 – tWP 8 – 8 – 10 – 12 – tAH 0 – 0 – 0 – 0 – tDW 5 – 6 – 8 – 10 – tDH 0 – 0 – 0 – 0 – tWZ – 6 – 6 – 6 – 8 tOW 1 – 1 – 1 – 2 – tBW 8 – 8 – 9 – 12 – ns ns ns ns ns ns ns ns ns ns ns Write waveform 1 (WE controlled) Address CE LB, UB tAS tWC tCW tBW tAW tWP tWR WE DataIN DataOUT Data undefined tWZ tDW Data valid tDH tOW high Z Write waveform 2 (CE controlled) Address CE tAS LB, UB WE tWC tCW tAW tBW tWP tDW tWR tDH DataIN DataOUT tCLZ high Z tWZ Data undefined Data valid high Z tOW Notes 5 4, 5 4, 5 DID 11-20011-A. 5/22/00 ALLIANCE SEMICONDUCTOR 5 5 Page

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