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Número de pieza | CS52843EDR8 | |
Descripción | Current Mode PWM Control Circuit | |
Fabricantes | Cherry Semiconductor Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CS52843EDR8 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
No Preview Available ! CS52843
Current Mode PWM Control Circuit
Description
The CS52843 provides all the nec-
essary features to implement off-
line fixed frequency current-mode
control with a minimum number
of external components.
The CS52843 incorporates a new
precision temperature-controlled
oscillator to minimize variations in
frequency. An undervoltage lock-
out ensures that VREF is stabilized
before the output stage is enabled.
In the CS52843 turn on is at 8.4V
and turn off at 7.6V.
Other features include low start-up
current, pulse-by-pulse current lim-
iting, and a high-current totem pole
output for driving capacitive loads,
such as gate of a power MOSFET.
The output is low in the off state,
consistent with N-channel devices.
Absolute Maximum Ratings
Supply Voltage (ICC<30mA) ..........................................................Self Limiting
Supply Voltage (Low Impedance Source)...................................................30V
Output Current ...............................................................................................±1A
Output Energy (Capacitive Load) .................................................................5µJ
Analog Inputs (VFB, VSENSE)...........................................................-0.3V to 5.5V
Error Amp Output Sink Current...............................................................10mA
Lead Temperature Soldering
Reflow (SMD styles only) ...........60 sec. max above 183°C, 230°C peak
Block Diagram
VCC VCC Undervoltage Lock-out
34V
Gnd
VFB
COMP
OSC
Sense
8.4V/7.6V
Set/ 5.0 Volt
Reset Reference
Error
Amplifier
-
+
2.50V
OUTPUT
R ENABLE
R
Oscillator
2R
R
S
R
1V
Current PWM
Sensing Latch
Comparator
NOR
Internal
Bias
VCC Pwr
VREF
VOUT
Pwr Gnd
Features
s Optimized for Off-line
Control
s Internally Temperature
Compensated Oscillator
s VREF Stabilized before
Output Stage is Enabled
s Very Low Start-up Current
300 µA (typ)
s Pulse-by-pulse Current
Limiting
s Improved Undervoltage
Lockout
s Double Pulse Suppression
s 2% 5 Volt Reference
s High Current Totem Pole
Output
Package Options
8L SO Narrow
COMP 1
VFB 2
8 VREF
7 VCC
Sense 3
6 VOUT
OSC 4
5 Gnd
14L SO Narrow
COMP 1
NC 2
VFB 3
NC 4
Sense 5
NC 6
OSC 7
14 VREF
13 NC
12 VCC
11 VCC Pwr
10 VOUT
9 Pwr Gnd
8 Gnd
Rev. 12/23/97
Cherry Semiconductor Corporation
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Email: [email protected]
Web Site: www.cherry-semi.com
1 A ® Company
1 page Circuit Description
When the power supply sees a sudden large output cur-
rent increase, the control voltage will increase allowing the
duty cycle to momentarily increase. Since the duty cycle
tends to exceed the maximum allowed to prevent trans-
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
VOSC
OSC
RESET
Toggle
F/F Output
EA Output
Switch
Current
VCC
IO
VO
Setting the Oscillator
The times Tc and Td can be determined as follows:
( )tc = RTCT ln
VREF - VLOWER
VREF - VUPPER
( )td = RTCT ln
VREF - IdRT - VLOWER
VREF - IdRT - VUPPER
Substituting in typical values for the parameters in the
above formulas:
VREF = 5.0V, VUPPER = 2.7V, VLOWER = 1.0V, Id = 8.3mA,
then
tc ≈ 0.5534RTCT
( )td = RTCT ln
2.3 - 0.0083 RT
4.0 - 0.0083 RT
Figure 2: Timing Diagram
For better accuracy RT should be ≥10kΩ.
VREF
OSC
Gnd
RT
CT
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
Vupper
Vlower
tc td
Sawtooth Mode
LARGE RT (≈10kΩ)
VOSC
Triangular Mode
SMALL RT (≈700kΩ)
Internal Clock
VREF
Internal Clock
Figure 3: Oscillator Timing Network and Parameters
5
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet CS52843EDR8.PDF ] |
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