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Número de pieza | A62S6316 | |
Descripción | 64K X 16 BIT LOW VOLTAGE CMOS SRAM | |
Fabricantes | AMIC Technology | |
Logotipo | ||
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Preliminary
A62S6316 Series
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
64K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
History
Initial issue
Change access times from 70/100 ns to 55/70 ns(max.)
Change dynamic operating current from 80/70mA to 40mA
Modify TSOP 44L (Type II) package outline drawing
Modify truth table
Change dynamic operating current from 40mA to 50mA(max.)
Modify TSOP 44L (Type II) package outline drawing and
Dimensions
Add mini BGA package outline dimensions symbol E2 min.
and max.
Issue Date
October 8, 1998
February 12, 1999
June 9, 1999
June 21, 1999
November 9, 1999
August 12, 2002
Remark
Preliminary
PRELIMINARY (August, 2002, Version 0.5)
AMIC Technology, Inc.
1 page www.DataSheet4U.com
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -25°C to +85°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
A62S6316 Series
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.3V, GND = 0V)
Symbol
Parameter
ILI
Input Leakage
Current
ILO
Output Leakage
Current
A62S6316-55S/70S
Min.
Max.
-1
-1
Active Power
ICC Supply Current
-
5
A62S6316-55SI/70SI
Min.
Max.
-1
-1
-5
Unit Conditions
µA VIN = GND to VCC
CE = VIH or LB = VIH or
µA HB = VIH or OE = VIH or
WE = VIH
VI/O = GND to VCC
mA CE = VIL, II/O = 0mA
ICC1
Dynamic
Operating
Current
ICC2
Min. Cycle, Duty = 100%
- 50 - 50 mA CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC,
- 20 - 20 mA VIL = 0V, f = 1MHz,
II/O = 0 mA
ISB - 0.5 - 0.5 mA CE = VIH
Standby Power
ISB1 Supply Current
-
15
-
30 µA CE ≥ VCC - 0.2V
VIN ≥ 0V
VOL
Output Low
Voltage
- 0.4 - 0.4 V IOL = 2.1mA
VOH
Output High
Voltage
2.2
-
2.2
- V IOH = -1.0mA
PRELIMINARY (August, 2002, Version 0.5)
4
AMIC Technology, Inc.
5 Page www.DataSheet4U.com
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
tWC
tAW
tCW
tBW2
tWP
tDW
A62S6316 Series
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (August, 2002, Version 0.5)
10
AMIC Technology, Inc.
11 Page |
Páginas | Total 15 Páginas | |
PDF Descargar | [ Datasheet A62S6316.PDF ] |
Número de pieza | Descripción | Fabricantes |
A62S6316 | 64K X 16 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
A62S6316G-55S | 64K X 16 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
A62S6316G-55SI | 64K X 16 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
A62S6316G-70S | 64K X 16 BIT LOW VOLTAGE CMOS SRAM | AMIC Technology |
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