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PDF A3980KLP Data sheet ( Hoja de datos )

Número de pieza A3980KLP
Descripción Automotive DMOS Microstepping Driver with Translator
Fabricantes Allegro MicroSystems 
Logotipo Allegro MicroSystems Logotipo



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A3980
Automotive DMOS Microstepping Driver with Translator
Package LP
SENSE1 1
SR 2
DIR 3
OUT1A 4
PFD 5
RC1 6
AGND 7
REF 8
÷8
RC2 9
VDD 10 VDD
OUT2A 11
MS2 12
MS1 13
SENSE2 14
VBB1 28 VBB1
27 SLEEP
26 ENABLE
25 OUT1B
24 CP2
23 CP1
22 VCP
21 PGND
Reg 20 VREG
19 STEP
18 OUT2B
17 FF2
16 FF1
VBB2 15 VBB2
Approximate Scale 1:1
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, 500 ms,VBB .....................50 V
Logic Supply Voltage, VDD................................7.0 V
Logic Input Voltage
VIN ................................. –0.3 V to VDD + 0.3 V
(tW < 30 ns) ....................... –1.0 V to VDD + 1 V
Sense Voltage, VSENSE .......................................0.5 V
Reference Voltage, VREF ……….. ........... 0 V to VDD
Package Power Dissipation (TA = +25ºC), PD
"High-K" PCB1 ..............................RθJA28ºC/W
Typical PCB2..................................RθJA38ºC/W
Operating Temperature Range
Junction Temperature, TJ ...........–40°C to +150°C
Storage Temperature, TS ..........–55°C to +150°C
1Measured on a JEDEC-standard "High-K" 4-layer PCB.
2Measured on a typical two-sided PCB with 3 in.2 copper
ground area.
The A3980 is a complete microstepping motor driver with built-in
translator for easy operation. It is designed to operate bipolar stepper
motors in full-, half-, eighth-, and sixteenth-step modes, at up to 35 V
and ±1 A. The A3980 includes a xed off-time current regulator which
has the ability to operate in slow, fast, or mixed decay modes. This
results in reduced audible motor noise, increased step accuracy, and
reduced power dissipation.
The translator is the key to the easy implementation of the A3980.
Simply inputting one pulse on the step input drives the motor one
microstep. There are no phase sequence tables, high frequency control
lines, or complex interfaces to program. The A3980 interface is an ideal
t for applications where a complex µP is unavailable or overburdened.
Internal synchronous rectication control circuitry is provided to
improve power dissipation during PWM operation.
Internal circuit protection includes: thermal shutdown with hysteresis,
overvoltage lockout (OVLO), undervoltage lockout (UVLO), and
crossover current protection. Special power-up sequencing is not
required. In addition, two diagnostic fault ags provide indication of
shorts or opens on the motor windings.
The A3980 is supplied in a low-prole (1.1 mm) 28L TSSOP with
exposed thermal pad (part number sufx LP).
FEATURES
Typical application up to ±1 A, 35 V output rating
Low RDS(ON) outputs, 0.67 source, 0.54 sink typical
Automatic current decay mode detection/selection
3.0 V to 5.5 V logic supply voltage range
Mixed, fast, and slow current decay modes
Synchronous rectication for low power dissipation
Internal OVLO, UVLO, and thermal shutdown circuitry
Crossover current protection
Short to supply/ground and short/open load diagnostics
APPLICATIONS
Automotive stepper motors
Engine management
Headlamp positioning
Use the following complete part number when ordering:
Part Number
Package
Description
A3980KLP
28-pin, TSSOP
Exposed thermal pad

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A3980KLP pdf
A3980
Automotive DMOS Microstepping Driver with Translator
Logic Interface Timing Diagram
tSTPH
STEP
MS1, MS2,
or DIR
tSU tH
tEN
SLEEP
tSTPL
Table 1. Microstep Resolution Truth Table
MS1 MS2
Microstep Resolution
LL
Full Step
HL
Half Step
LH
HH
Eighth Step
Sixteenth Step
Table 2. Fault Report by Fault Flags
FF1 FF2
Fault
L
L
UVLO, OVLO, Overtemperature,
Open Load, or Shorted Load
HL
Short to Ground
LH
Short to Supply
HH
None
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
5

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A3980KLP arduino
A3980
Automotive DMOS Microstepping Driver with Translator
mixed decay mode, as shown in gures 5 through 8. As the
trip point is reached, the A3980 goes into fast decay mode
until the voltage on the RC pin decays to the same level as the
voltage applied to the PFD pin. The duration of time that the
bridge operates in fast decay mode, tFD (ns), is estimated by
× ×tFD = RT CT ln[0.6 (VDD VPFD)]
over a range of values from CT= 470 pF to 1500 pF and from
RT = 12 kto 100 k.
After this fast decay period, the A3980 switches to slow
decay mode for the remainder of the xed off-time period.
Synchronous Rectication. When a PWM-off cycle
is triggered by an internal xed-off-time cycle, load current
recirculates according to the decay mode selected by the
control logic. The synchronous rectication feature turns on
the appropriate FETs during current decay, and effectively
shorts out the body diodes with the low DMOS RDSON. This
reduces power dissipation signicantly, and eliminates the
need for external Schottky diodes. Synchronous rectication
has two modes: Active mode and Disabled mode (described
below).
Active Mode. When the input on the SR terminal is set
at logic low, Active mode is enabled. This mode allows
synchronous rectication to occur, but when a zero current
level is detected, it also prevents reversal of the load current
by turning off synchronous rectication. This prevents the
motor winding from conducting in the reverse direction.
Disabled Mode. When the input on the SR terminal is set
at logic high, Disabled mode takes effect. This mode disables
synchronous rectication. This mode is typically used when
external diodes are required to transfer power dissipation
from the A3980 package to the external diodes.
Shutdown. In the event of an overtemperature fault or
an undervoltage fault on VREG, the DMOS outputs of the
A3980 are disabled until the fault condition is removed. In
the case of an overvoltage fault, the sink DMOS FETs are
switched on, and the source FETs off. At power-up, and in
the event of low VDD, the UVLO circuit disables the DMOS
outputs until VDD reaches the minimum level. Once VDD is
above the minimum level, the translator resets to the Home
state and the DMOS outputs are re-enabled.
Thermal Protection. All drivers are turned off when the
junction temperature reaches the thermal shutdown value,
typically 170°C. This is intended only to protect the A3980
from failures due to excessive junction temperatures. Ther-
mal protection will not protect the A3980 from continuous
short circuits, and additional fault diagnostics are integrated for
this purpose. Thermal shutdown has a hysteresis of approxi-
mately 15°C.
Diagnostic Features. The A3980 includes monitor
circuits that can detect shorts to VBB, shorts to ground, and
shorted or open circuit load. Short circuits are detected by
monitoring the voltage across the driving DMOS FETs and
the open load is detected by monitoring the phase current
when the motor is in the Home microstep position. All fault
detection takes place following a delay after the blank time.
Short to VBB. A short from any of the motor connections
to the battery or VBB connection is detected by monitoring
the voltage across the bottom FETs in each full-bridge. When
the FET is on, the voltage should be no greater than the
VDSLT value dened in the Electrical Characteristics table.
Short to Ground. A short from any of the motor connec-
tions to ground is detected by monitoring the voltage across
the top FETs in each full-bridge. When the FET is turned
on, the voltage should be no greater than the VDSHT value
dened in the Electrical Characteristics table.
Shorted Load. A short across the load is detected by
monitoring the voltage across both the top and bottom FETs
in each full-bridge.
Short Fault Operation. Because motor capacitance may
cause the measured voltages to show a fault as the full-bridge
switches, voltages are not sampled until after the blank
time plus an internally-generated delay, tSCT. Once a short
circuit has been detected, all outputs for the faulty phase are
disabled until the next step command. At the next step com-
mand, the outputs are re-enabled and the voltage across the
FET is resampled.
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
11

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