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PDF A3967 Data sheet ( Hoja de datos )

Número de pieza A3967
Descripción MICROSTEPPING DRIVER WITH TRANSLATOR
Fabricantes Allegro MicroSystems 
Logotipo Allegro MicroSystems Logotipo



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A3967
Microstepping Driver with Translator
Features and Benefits
±750 mA, 30 V output rating
Satlington® sink drivers
Automatic current-decay mode detection/selection
3.0 to 5.5 V logic supply voltage range
Mixed, fast, and slow current-decay modes
Internal UVLO and thermal shutdown circuitry
Crossover-current protection
Package: 24-pin SOIC with internally
fused pins (suffix LB)
Not to scale
Description
TheA3967 is a complete microstepping motor driver with built-
in translator. It is designed to operate bipolar stepper motors in
full-, half-, quarter-, and eighth-step modes, with output drive
capability of 30 V and ±750 mA. The A3967 includes a fixed
off-time current regulator that has the ability to operate in slow,
fast, or mixed current-decay modes. This current-decay control
scheme results in reduced audible motor noise, increased step
accuracy, and reduced power dissipation.
The translator is the key to the easy implementation of the
A3967. By simply inputting one pulse on the STEP input the
motor will take one step (full, half, quarter, or eighth depending
on two logic inputs). There are no phase-sequence tables, high-
frequency control lines, or complex interfaces to program. The
A3967 interface is an ideal fit for applications where a complex
μP is unavailable or over-burdened.
Internal circuit protection includes thermal shutdown with
hysteresis, under-voltage lockout (UVLO) and crossover-
current protection. Special power-up sequencing is not
required.
The A3967 is supplied in a 24-pin SOIC, which is lead (Pb)
free with 100% matte tin leadframe plating. Four pins are
fused internally for enhanced thermal dissipation. The pins
are at ground potential and need no insulation.
LOGIC
SUPPLY
VCC
14
REF.
SUPPLY
REF
1
RC1
23
STEP 10
DIR 11
RESET 22
MS1 12
MS2 13
Functional Block Diagram
UVLO
AND
FAULT
DETECT
÷8 DAC
+-
SENSE
PWM LATCH
BLANKING
MIXED DECAY
3 PWM TIMER
SLEEP 3
ENABLE 15
VPF
24
PFD
2
RC2
PWM TIMER
3 PWM LATCH
BLANKING
MIXED DECAY
DAC
+-
67
18 19
VBB1
20
LOAD
SUPPLY
OUT1A
16
OUT1B
21
SENSE1
17
5
VBB2
OUT2A
9
OUT2B
4
SENSE2
8
Dwg. FP-050-3A
26184.24H

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A3967 pdf
A3967
Microstepping Driver with Translator
Functional Description
Device Operation. The A3967 is a complete microstep-
ping motor driver with built in translator for easy operation
with minimal control lines. It is designed to operate bipolar
stepper motors in full-, half-, quarter- and eighth-step
modes. The current in each of the two output full bridges
is regulated with xed off time pulse-width modulated
(PWM) control circuitry. The full-bridge current at each
step is set by the value of an external current sense resis-
tor (RS), a reference voltage (VREF), and the DACs output
voltage controlled by the output of the translator.
At power up, or reset, the translator sets the DACs and
phase current polarity to initial home state (see gures for
home-state conditions), and sets the current regulator for
both phases to mixed-decay mode. When a step command
signal occurs on the STEP input the translator automati-
cally sequences the DACs to the next level (see table 2 for
the current level sequence and current polarity). The mic-
rostep resolution is set by inputs MS1 and MS2 as shown in
table 1. If the new DAC output level is lower than the pre-
vious level the decay mode for that full bridge will be set
by the PFD input (fast, slow or mixed decay). If the new
DAC level is higher or equal to the previous level then the
decay mode for that Full bridge will be slow decay. This
automatic current-decay selection will improve microstep-
ping performance by reducing the distortion of the current
waveform due to the motor BEMF.
Reset Input (RESET). The RESET input (active low)
sets the translator to a predened home state (see gures
for home state conditions) and turns off all of the outputs.
STEP inputs are ignored until the RESET input goes high.
Step Input (STEP). A low-to-high transition on the
STEP input sequences the translator and advances the
motor one increment. The translator controls the input to
the DACs and the direction of current ow in each wind-
ing. The size of the increment is determined by the state of
inputs MS1 and MS2 (see table 1).
Microstep Select (MS1 and MS2). Input terminals
MS1 and MS2 select the microstepping format per
table 1. Changes to these inputs do not take effect until the
STEP command (see gure).
Direction Input (DIR). The state of the DIRECTION
input will determine the direction of rotation of the motor.
Internal PWM Current Control. Each full bridge is
controlled by a xed off-time PWM current-control cir-
cuit that limits the load current to a desired value (ITRIP).
Initially, a diagonal pair of source and sink outputs are
enabled and current ows through the motor winding and
RS. When the voltage across the current-sense resistor
equals the DAC output voltage, the current-sense compara-
tor resets the PWM latch, which turns off the source driver
(slow-decay mode) or the sink and source drivers (fast- or
mixed-decay modes).
The maximum value of current limiting is set by the
selection of RS and the voltage at the VREF input with a
transconductance function approximated by:
ITRIPmax = VREF/8RS
The DAC output reduces the VREF output to the cur-
rent-sense comparator in precise steps (see table 2 for %
ITRIPmax at each step).
ITRIP = (% ITRIPmax/100) x ITRIPmax
Fixed Off-Time. The internal PWM current-control
circuitry uses a one shot to control the time the driver(s)
remain(s) off. The one shot off-time, toff, is determined by
the selection of an external resistor (RT) and capacitor (CT)
connected from the RC timing terminal to ground. The off
time, over a range of values of CT = 470 pF to 1500 pF and
RT = 12 kΩ to 100 kΩ is approximated by:
toff = RTCT
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5

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A3967 arduino
A3967
STEP
INPUT
Microstepping Driver with Translator
Half Step Operation
MS1 = H, MS2 = L, DIR = H
100%
70.7%
PHASE 1
CURRENT
–70.7%
–100%
100%
70.7%
PHASE 2
CURRENT
–70.7%
–100%
Dwg. WK-004-18
The mixed-decay mode is controlled by the percent fast decay voltage (VPFD). If the volt-
age at the PFD input is greater than 0.6VCC then slow-decay mode is selected. If the volt-
age on the PFD input is less than 0.21VCC then fast-decay mode is selected. Mixed decay
is between these two levels.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11

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