A3949SLB Datasheet PDF - Allegro MicroSystems
| Part Number | A3949SLB | |
| Description | DMOS Full-Bridge Motor Driver | |
| Manufacturers | Allegro MicroSystems | |
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A3949
DMOS Full-Bridge Motor Driver
Features and Benefits
▪ Single supply operation
▪ Very small outline package
▪ Low RDS(ON) outputs
▪ Sleep function
▪ Internal UVLO
▪ Crossover current protection
▪ Thermal shutdown protection
Packages:
Package LB, 16-pin SOIC
with internally fused pins
Description
Designed for PWM (pulse width modulated) control of DC
motors, the A3949 is capable of peak output currents to ±2.8 A
and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use
in controlling the speed and direction of a DC motor with
externally applied PWM control signals. Internal synchronous
rectification control circuitry is provided to reduce power
dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, undervoltage monitoring of VBB and VCP , and
crossover current protection.
TheA3949 is supplied in a power package, a 16-pin plastic SOIC
with a copper batwing tab (part number suffix LB).The packages
are lead (Pb) free, with 100% matte tin leadframes.
Not to scale
Functional Block Diagram
.22 μF
25 V
VREG
0.1 μF
CP1
CP2
MODE
PHASE
ENABLE
SLEEP
Low Side
Gate Supply
OSC
Charge
Pump
Control
Logic
DMOS Full Bridge
VCP
VBB
0.1 μF
Load
Supply
0.1 μF
100 μF
OUTA
OUTB
SENSE
GND
GND
29319.47i
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A3949
DMOS Full-Bridge Motor Driver
Functional Description
VREG. This supply voltage is used to operate the sink-
side DMOS outputs. VREG is internally monitored and in
the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 F
capacitor to ground.
Charge Pump. The charge pump is used to generate a
supply above VBB to drive the source-side DMOS gates. A
0.1 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP voltage is internally monitored,
and in the case of a fault condition, the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed.
At power-up, the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize
power consumption when the A3949 is not in use. This
disables much of the internal circuitry, including the low-side
gate supply and the charge pump. A logic low on this pin
puts the device into Sleep mode. A logic high allows normal
operation. After coming out of Sleep mode, the user should
wait 1 ms before applying PWM signals, to allow the charge
pump to stabilize.
Braking. The braking function is implemented by driv-
ing the device in slow decay mode via the MODE pin, and
applying an enable chop command. Because it is possible to
drive current in both directions through the DMOS switches,
this configuration effectively shorts out the motor-generated
BEMF, as long as the enable chop mode is asserted on the
ENABLE pin. The maximum current can be approximated
by VBEMF / RL. Care should be taken to insure that the maxi-
mum ratings of the device are not exceeded in worse case
braking situations of high speed and high inertial loads.
Control Logic Table
PHASE ENABLE MODE SLEEP OUTA OUTB
Function
1 1X1HL
Forward
0 1X1 LH
Reverse
X0 1 1 L L
Brake (slow decay)
1 0 0 1 LH
Fast decay SR*
0 0 0 1HL
Fast decay SR*
X X X 0 Hi-Z Hi-Z
Sleep mode
* To prevent reversal of current during fast decay SR (synchronous rectification), the outputs
go to the high impedance state as the current approaches zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for A3949SLB electronic component. |
| Information | Total 7 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ A3949SLB.PDF Datasheet ] | |
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