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A29L160UM-90 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A29L160UM-90
Beschreibung 2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only/ Boot Sector Flash Memory
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 45 Seiten
A29L160UM-90 Datasheet, Funktion
Preliminary
A29L160 Series
2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Document Title
2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
July 31, 2002
Remark
Preliminary
PRELIMINARY (July, 2002, Version 0.0)
AMIC Technology, Inc.






A29L160UM-90 Datasheet, Funktion
A29L160 Series
Absolute Maximum Ratings*
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . .0°C to + 70°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . . . . . . . 0°C to + 70°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . . . -0.5 to +12.5V
All other pins (Note 1) . . . . . . . . . . . . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . . . 200mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot
VSS to -2.0V for periods of up to 20ns. Maximum DC
voltage on input and I/O pins is VCC +0.5V. During
voltage transitions, input or I/O pins may overshoot to
VCC +2.0V for periods up to 20ns.
2. Minimum DC input voltage on A9, OE and RESET is -
0.5V. During voltage transitions, A9, OE and RESET
may overshoot VSS to -2.0V for periods of up to 20ns.
Maximum DC input voltage on A9 is +12.5V which may
overshoot to 14.0V for periods up to 20ns.
3. No more than one output is shorted at a time. Duration
of the short circuit should not be greater than one
second.
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of
this device at these or any other conditions above
those indicated in the operational sections of these
specification is not implied or intended. Exposure to
the absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Ranges
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . . +2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Device Bus Operations
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location. The
register is composed of latches that store the commands,
along with the address and data information needed to
execute the command. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device. The appropriate
device bus operations table lists the inputs and control
levels required, and the resulting output. The following
subsections describe each of these operations in further
detail.
Table 1. A29L160 Device Bus Operations
Operation
CE OE WE RESET
A0 – A19
(Note 1)
I/O0 - I/O7
I/O8 - I/O15
BYTE =VIH BYTE =VIL
Read
L
LH
H
AIN
DOUT
DOUT
I/O8~I/O4=High-Z
I/O15=A-1
Write
L HL H
AIN
DIN DIN
High-Z
CMOS Standby
VCC ± 0.3 V X X VCC ± 0.3 V
X
High-Z
High-Z
High-Z
Output Disable
L HH H
X
High-Z
High-Z
High-Z
Hardware Reset
X XX L
X
High-Z
High-Z
High-Z
Sector Protect
(See Note 2)
L
HL
VID
Sector Address,
A6=L, A1=H, A0=L
DIN
X
X
Sector Unprotect
(See Note 2)
L
HL
VID
Sector Address,
A6=H, A1=H, A0=L
DIN
X
X
Temporary Sector
Unprotect
X
XX
VID
AIN DIN DIN
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5V, X = Don't Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Notes:
1. Addresses are A19:A0 in word mode (BYTE=VIH), A19: A-1 in byte mode (BYTE=VIL).
2. See the “Sector Protection/Unprotection” section and Temporary Sector Unprotect for more information.
PRELIMINARY (July, 2002, Version 0.0)
5
AMIC Technology, Inc.

6 Page









A29L160UM-90 pdf, datenblatt
A29L160 Series
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
Sector protection / unprotection can be implemented via two
methods. The primary method requires VID on the
RESETpin only, and can be implemented either in-system or
via programming equipment. Figure 2 shows the algorithm
and the Sector Protect / Unprotect Timing Diagram illustrates
the timing waveforms for this feature. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle. The alternate
method must be implemented using programming
equipment. The procedure requires a high voltage (VID) on
address pin A9 and the control pins.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See "Autoselect Mode" for details.
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
VCC power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE =VIL,
CE = VIH or WE = VIH. To initiate a write cycle, CE and
WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of
WE . The internal state machine is automatically reset to
reading array data on the initial power-up.
Temporary Sector Unprotect
This feature allows temporary unprotection of previous
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID.
During this mode, formerly protected sectors can be
programmed or erased by selecting the sector addresses.
Once VID is removed from the RESET pin, all the previously
protected sectors are protected again. Figure 1 shows the
algorithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
START
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
Figure 1. Temporary Sector Unprotect Operation
PRELIMINARY (July, 2002, Version 0.0)
11
AMIC Technology, Inc.

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