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A29DL324TG-90 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A29DL324TG-90
Beschreibung 32M-Bit CMOS Low Voltage Dual Operation Flash Memory 4M-Byte by 8-Bit (Byte Mode) / 2M-Word by 16-Bit (Word Mode)
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A29DL324TG-90 Datasheet, Funktion
A29DL324 Series
32M-Bit CMOS Low Voltage Dual Operation Flash Memory
Preliminary 4M-Byte by 8-Bit (Byte Mode) / 2M-Word by 16-Bit (Word Mode)
Features
n Two bank organization enabling simultaneous execution of
erase / program and read
n Bank organization: 2 banks (16 Mbits + 16 Mbits)
n Memory organization:
- 4,194,304 words x 8 bits (BYTE mode)
- 2,097,152 words x 16 bits (WORD mode)
n Sector organization:
71 sectors (8 Kbytes / 4 Kwords × 8 sectors, 64 Kbytes /
32 Kwords × 63 sectors)
n 2 types of sector organization
- T type: Boot sector allocated to the highest address
(sector)
- B type: Boot sector allocated to the lowest address
(sector)
n 3-state output
n Automatic program
- Program suspend / resume
n Unlock bypass program
n Automatic erase
- Chip erase
- Sector erase (sectors can be combined freely)
n Erase suspend / resume
n Program / Erase completion detection
- Detection through data polling and toggle bits
- Detection through RY/ BY pin
n Sector group protection
- Any sector group can be protected
- Any protected sector group can be temporary
unprotected
n Sectors can be used for boot application
n Hardware reset and standby using RESET pin
n Automatic sleep mode
n Boot block sector protect by WP (ACC) pin
n Conforms to common flash memory interface (CFI)
n Extra One Time Protect Sector provided
Part No.
A29DL324
Access
time
(Max.)
90ns
Operating
supply
voltage
2.7V~
3.6V
Power supply current
(Active mode)
(Max.)
16mA 30mA
Standby
current
(Max.)
5A
n Operating ambient temperature: -40 to 85°C
n Program / erase time
- Program: 9.0 µs / byte (TYP.)
11.0 µs / word (TYP.)
- Sector erase: 0.7 s (TYP.)
n Number of program / erase: 1,000,000 times (MIN.)
n Package options
- 48-pin TSOP (I) or 63-ball TFBGA
General Description
The A29DL324 is a flash memory organized of 33,554,432
bits and 71 sectors. Sectors of this memory can be erased
at a low voltage (2.7 to 3.6 V) supplied from a single power
source, or the contents of the entire chip can be erased.
Two modes of memory organization, BYTE mode
(4,194,304 words × 8 bits) and WORD mode (2,097,152
words × 16 bits), are selectable so that the memory can be
programmed in byte or word units.
The A29DL324 can be read while its contents are being
erased or programmed. The memory cell is divided into two
banks. While sectors in one bank are being erased or
programmed, data can be read from the other bank thanks
to the simultaneous execution architecture. The banks are
8 Mbits and 24 Mbits.
This flash memory comes in two types. The T type has a
boot sector located at the highest address (sector) and the
B type has a boot sector at the lowest address (sector).
Because the A29DL324 enables the boot sector to be
erased, it is ideal for storing a boot program. In addition,
program code that controls the flash memory can be also
stored, and the program code can be programmed or
erased without the need to load it into RAM. Eight small
sectors for storing parameters are provided, each of which
can be erased in 8 Kbytes units.
Once a program or erase command sequence has been
executed, an automatic program or automatic erase
function internally executes program or erase and
verification automatically.
Because the A29DL324 can be electrically erased or
programmed by writing an instruction, data can be
reprogrammed on-board after the flash memory has been
installed in a system, making it suitable for a wide range of
applications.
PRELIMINARY (May, 2002, Version 0.0)
1
AMIC Technology, Inc.






A29DL324TG-90 Datasheet, Funktion
A29DL324 Series
Read Operation
The read operation is controlled by the OE and /OE. The
/CE is used to select a device, and the OE controls data
output. The following three access times are used
depending on the condition.
- Address access time (tACC): Time until valid data is
output after an address has been determined
(however, after CE ).
- CE access time (tCE): Time until valid data is output
after CE has been determined (however, after
address).
- OE access time (tOE): Time until valid data is output
after OE has been determined (however, OE must
be input after tACC-tOE, tCE-tOE after address and CE
have been determined).
On power-up, the device is automatically set in the read
mode. To read the device without changing address
immediately after power application, either execute
hardware reset or briefly lower CE to VIL from VIH.
For the timing waveform, refer to Timing Waveform for
Read Cycle (1).
Write Operation
The operation of the device is controlled by writing
commands to the registers. The command register is a
function that latches the address and data necessary for
executing an instruction and does not occupy the memory
area.
If an illegal address or data is written or if an address or
data is written in the wrong sequence, the device is reset to
the read mode.
Standby Mode
The standby mode is set when VIH is input to the CE . The
current consumption in the standby mode can be lowered to
5 µA or less in two ways.
One is to use CE and RESET . Input VCC ± 0.3 V to CE
and RESET . However, while automatic programming or
erasing is being executed, the operating supply current
(ICC2) does not decrease to 5µA or lower even if CE = VIH.
If a read operation is executed in the standby mode, data is
output at CE access time.
The other is to input GND ± 0.3 V to the RESET . At this
time, the level of CE is VIH or VIL. In this case, tRH is
required for the device to return to the read mode from the
standby mode.
For the timing waveform, refer to Timing Waveform for
Read Cycle (2).
Hardware Reset Pin
The device is reset to the read mode if VIL is input to the
RESET for the duration of tRP and VIH for the duration of
tRH. While VIL is being input to the RESET , all commands
are ignored, and the output pins go into a Hi-Z state. If the
voltage on RESET is kept to GND ± 0.2 V at this time, the
current consumption can be lowered to 5µA or less. If VIH is
input to the RESET , tREADY is required until data is output.
For the timing waveform, refer to Timing Waveform for
Read Cycle (2).
Output Disable Mode
Output from the device is disabled (Hi-Z state) if VIH is input
to the OE .
Sector Group Protection
Protect the sector group by using a command. OE or WE
control is no need.
Temporary Sector Group Unprotect
Protection of a sector group can be temporarily canceled.
When VID is input to RESET , the temporary sector group
unprotect mode is set. If a protected sector is selected in
this mode, it can be programmed or erased. If the mode is
canceled, the sector group is protected again.
For the timing waveform, refer to Timing Waveform for
Temporary Sector Group Unprotect.
Product ID
Read the product ID code by using a command.
Automatic Sleep Mode
The automatic sleep mode is used to reduce the power
consumption substantially during a read operation.
If an address is held longer than the minimum read
cycle time (tRC), the sleep mode (low power
consumption mode) is automatically set. In this mode, the
output data is latched and continuously output.
In the automatic sleep mode, CE , WE , and OE do not
have to be controlled. At this time, the current consumption
decreases to 5µA or less. During dual operation,
however, the current consumption is power supply
current (ICC6, ICC7).
If the address is changed, the automatic sleep mode
is canceled automatically, the device returns to the
read mode, and the data of the newly input address is
output.
PRELIMINARY (May, 2002, Version 0.0)
6
AMIC Technology, Inc.

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A29DL324TG-90 pdf, datenblatt
A29DL324 Series
Table 5. A29DL324 Top Boot Sector Group Address Table
Sector Group
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
SGA9
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
SGA24
A20 A19 A18 A17 A16 A15 A14 A13 A12
Size
0 0 0 0 0 0 X X X 64 KB (1 Sector)
0 0 0 0 0 1 X X X 192 KB (3 Sectors)
10
11
0 0 0 1 X X X X X 256 KB (4 Sectors)
0 0 0 1 X X X X X 256 KB (4 Sectors)
0 0 1 1 X X X X X 256 KB (4 Sectors)
0 1 0 0 X X X X X 256 KB (4 Sectors)
0 1 0 1 X X X X X 256 KB (4 Sectors)
0 1 1 0 X X X X X 256 KB (4 Sectors)
0 1 1 1 X X X X X 256 KB (4 Sectors)
0 1 1 1 X X X X X 256 KB (4 Sectors)
1 0 0 1 X X X X X 256 KB (4 Sectors)
1 0 1 0 X X X X X 256 KB (4 Sectors)
1 0 1 1 X X X X X 256 KB (4 Sectors)
1 1 0 0 X X X X X 256 KB (4 Sectors)
1 1 0 1 X X X X X 256 KB (4 Sectors)
1 1 1 0 X X X X X 256 KB (4 Sectors)
1 1 1 1 0 0 X X X 192 KB (3 Sectors)
01
10
1 1 1 1 1 1 0 0 0 8 KB (1 Sector)
1 1 1 1 1 1 0 0 1 8 KB (1 Sector)
1 1 1 1 1 1 0 1 0 8 KB (1 Sector)
1 1 1 1 1 1 0 1 1 8 KB (1 Sector)
1 1 1 1 1 1 1 0 0 8 KB (1 Sector)
1 1 1 1 1 1 1 0 1 8 KB (1 Sector)
1 1 1 1 1 1 1 1 0 8 KB (1 Sector)
1 1 1 1 1 1 1 1 1 8 KB (1 Sector)
Remark X: VIH or VIL
Sector
FSA0
FSA1–FSA3
FSA4–FSA7
FSA8–FSA11
FSA12–FSA15
FSA16–FSA19
FSA20–FSA23
FSA24–FSA27
FSA28–FSA31
FSA32–FSA35
FSA36–FSA39
FSA40–FSA43
FSA44–FSA47
FSA48–FSA51
FSA52–FSA55
FSA56–FSA59
FSA60–FSA62
FSA63
FSA64
FSA65
FSA66
FSA67
FSA68
FSA69
FSA70
PRELIMINARY (May, 2002, Version 0.0)
12
AMIC Technology, Inc.

12 Page





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