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A29800UV-90 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A29800UV-90
Beschreibung 1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only/ Boot Sector Flash Memory
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A29800UV-90 Datasheet, Funktion
A29800 Series
Preliminary
1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
n 5.0V ± 10% for read and write operations
n Access times:
- 55/70/90 (max.)
n Current:
- 28mA read current (word mode)
- 20 mA typical active read current (byte mode)
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
n Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX15 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX15 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n Top or bottom boot block configurations available
n Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C
- Reliable operation for the life of the system
n Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
n Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
n Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
n Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data
n Package options
- 44-pin SOP or 48-pin TSOP (I)
General Description
The A29800 is a 5.0 volt only Flash memory organized as
1048,576 bytes of 8 bits or 524,288 words of 16 bits each. The
A29800 offers the RESET function. The 1024 Kbytes of data
are further divided into nineteen sectors for flexible sector erase
capability. The 8 bits of data appear on I/O0 - I/O7 while the
addresses are input on A1 to A18; the 16 bits of data appear on
I/O0~I/O15. The A29800 is offered in 44-pin SOP and 48-Pin
TSOP packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply. Additional
12.0 volt VPP is not required for in-system write or erase
operations. However, the A29800 can also be programmed in
standard EPROM programmers.
The A29800 has the first toggle bit, I/O6, which indicates whether
an Embedded Program or Erase is in progress, or it is in the
Erase Suspend. Besides the I/O6 toggle bit, the A29800 has a
second toggle bit, I/O2, to indicate whether the addressed sector
is being selected for erase. The A29800 also offers the ability to
program in the Erase Suspend mode. The standard A29800
offers access times of 55, 70 and 90 ns, allowing high-speed
microprocessors to operate without wait states. To eliminate bus
contention the device has separate chip enable ( CE ), write
enable ( WE ) and output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29800 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation.
PRELIMINARY (May, 2001, Version 0.0)
1
AMIC Technology, Inc.






A29800UV-90 Datasheet, Funktion
A29800 Series
Table 2. A29800 Top Boot Block Sector Address Table
Sector A18 A17 A16 A15 A14 A13 A12 Sector Size Address Range (in hexadecimal)
(Kbytes/
Kwords)
(x16)
(x8)
Address Range Address Range
SA0 0 0 0 0 X X X
64/32
00000h - 07FFFh 00000h - 0FFFFh
SA1 0 0 0 1 X X X
64/32
08000h - 0FFFFh 10000h - 1FFFFh
SA2 0 0 1 0 X X X
64/32
10000h - 17FFFh 20000h - 2FFFFh
SA3 0 0 1 1 X X X
64/32
18000h - 1FFFFh 30000h - 3FFFFh
SA4 0 1 0 0 X X X
64/32
20000h - 27FFFh 40000h - 4FFFFh
SA5 0 1 0 1 X X X
64/32
28000h - 2FFFFh 50000h - 5FFFFh
SA6 0 1 1 0 X X X
64/32
30000h - 37FFFh 60000h - 6FFFFh
SA7 0 1 1 1 X X X
64/32
38000h -3FFFFh 70000h -7FFFFh
SA8 1 0 0 0 X X X
64/32
40000h -47FFFh 80000h -8FFFFh
SA9 1 0 0 1 X X X
64/32
48000h -4FFFFh 90000h -9FFFFh
SA10 1 0 1 0 X X X
64/32
50000h - 57FFFh A0000h - AFFFFh
SA11 1 0 1 1 X X X
64/32
58000h - 5FFFFh B0000h - BFFFFh
SA12 1 1 0 0 X X X
64/32
60000h - 67FFFh C0000h - CFFFFh
SA13 1 1 0 1 X X X
64/32
68000h - 6FFFFh D0000h - DFFFFh
SA14 1 1 1 0 X X X
64/32
70000h - 77FFFh E0000h - EFFFFh
SA15 1 1 1 1 0 X X
32/16
78000h - 7BFFFh F0000h - F7FFFh
SA16 1 1 1 1 1 0 0
8/4 7C000h - 7CFFFh F8000h - F9FFFh
SA17 1 1 1 1 1 0 1
8/4 7D000h - 7DFFFh FA000h - FBFFFh
SA18 1 1 1 1 1 1 X
16/8 7E000h - 7FFFFh FC000h - FFFFFh
Note:
Address range is A18: A-1 in byte mod and A18: A0 in word mode. See the “Word/Byte Configuration” section for more
information.
PRELIMINARY (May, 2001, Version 0.0)
6
AMIC Technology, Inc.

6 Page









A29800UV-90 pdf, datenblatt
A29800 Series
Figure 3 illustrates the algorithm for the erase operation.
Refer to the Erase/Program Operations tables in the "AC
Characteristics" section for parameters, and to the Sector
Erase Operations Timing diagram for timing waveforms.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt
a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase
operation. Addresses are "don't cares" when writing the
Erase Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum of
20µs to suspend the erase operation. However, when the
Erase Suspend command is written during the sector erase
time-out, the device immediately terminates the time-out
period and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device "erase suspends" all
sectors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on I/O7
- I/O0. The system can use I/O7, or I/O6 and I/O2 together, to
determine if a sector is actively erasing or is erase-
suspended. See "Write Operation Status" for information on
these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-
suspended sectors. The system can determine the status of
the program operation using the I/O7 or I/O6 status bits, just
as in the standard program operation. See "Write Operation
Status" for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at
addresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation. See
"Autoselect Command Sequence" for more information.
The system must write the Erase Resume command
(address bits are "don't care") to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another Erase
Suspend command can be written after the device has
resumed erasing.
START
Write Erase
Command
Sequence
Data Poll
from System
No
Data = FFh ?
Embedded
Erase
algorithm in
progress
Yes
Erasure Completed
Note :
1. See the appropriate Command Definitions table for erase
command sequences.
2. See "I/O3 : Sector Erase Timer" for more information.
Figure 3. Erase Operation
PRELIMINARY (May, 2001, Version 0.0)
12
AMIC Technology, Inc.

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