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A29512L-70 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A29512L-70
Beschreibung 64K X 8 Bit CMOS 5.0 Volt-only/ Uniform Sector Flash Memory
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A29512L-70 Datasheet, Funktion
Preliminary
A29512 Series
64K X 8 Bit CMOS 5.0 Volt-only,
Uniform Sector Flash Memory
Document Title
64K X 8 Bit CMOS 5.0 Volt-only, Uniform Sector Flash Memory
Revision History
Rev. No. History
0.0 Initial issue
Issue Date
November 30, 2001
Remark
Preliminary
PRELIMINARY (November, 2001, Version 0.0)
AMIC Technology, Inc.






A29512L-70 Datasheet, Funktion
A29512 Series
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH all
the time during read operation. The internal state machine
is set for reading array data upon device power-up, or after
a hardware reset. This ensures that no spurious alteration
of the memory content occurs during the power transition.
No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid data
on the device data outputs. The device remains enabled for
read access until the command register contents are
altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to
the Read Operations Timings diagram for the timing
waveforms, lCC1 in the DC Characteristics table represents
the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE and CE to
VIL, and OE to VIH. An erase operation can erase one
sector, multiple sectors, or the entire device. The Sector
Address Tables indicate the address range that each sector
occupies. A "sector address" consists of the address inputs
required to uniquely select a sector. See the "Command
Definitions" section for details on erasing a sector or the
entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can
then read autoselect codes from the internal register (which
is separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
ICC2 in the Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section
for timing diagrams.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
The device enters the CMOS standby mode when the CE
is held at VCC ± 0.5V. (Note that this is a more restricted
voltage range than VIH.) The device enters the TTL standby
mode when CE is held at VIH. The device requires the
standard access time (tCE) before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represents the standby
current specification.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
PRELIMINARY (November, 2001, Version 0.0)
5
AMIC Technology, Inc.

6 Page









A29512L-70 pdf, datenblatt
A29512 Series
Table 4. A29512 Command Definitions
Command
Sequence
(Note 1)
Read (Note 5)
First
Second
Addr Data Addr Data
1 RA RD
Reset (Note 6)
1 XXX F0
Manufacturer ID
Autoselect
(Note 7) Device ID
4 555 AA
4 555 AA
2AA 55
2AA 55
Continuation ID
4 555 AA 2AA 55
Sector Protect Verify 4 555 AA 2AA 55
(Note 8)
Program
Chip Erase
4 555 AA
6 555 AA
2AA 55
2AA 55
Sector Erase
Erase Suspend (Note 9)
Erase Resume (Note 10)
6 555 AA
1 XXX B0
1 XXX 30
2AA 55
Bus Cycles (Notes 2 - 4)
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
555 90 X00 37
555 90 X01 A4
555 90 X03 7F
555 90 SA 00
X02 01
555 A0 PA PD
555 80 555 AA 2AA 55 555 10
555 80 555 AA 2AA 55 SA 30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A15 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A15 - A12 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more
information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend
mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50µs.
PRELIMINARY (November, 2001, Version 0.0)
11
AMIC Technology, Inc.

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