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A29512A Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A29512A
Beschreibung 64K X 8 Bit CMOS 5.0 Volt-only/ Uniform Sector Flash Memory
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A29512A Datasheet, Funktion
A29400 Series
Preliminary
512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
n 5.0V ± 10% for read and write operations
n Access times:
- 55/70/90 (max.)
n Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
n Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX7 sectors
- 8 Kword/ 4 KwordX2/ 16 Kword/ 32 KwordX7 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n Top or bottom boot block configurations available
n Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
General Description
The A29400 is a 5.0 volt only Flash memory organized as
524,288 bytes of 8 bits or 262,144 words of 16 bits each. The
A29400 offers the RESET function. The 512 Kbytes of data
are further divided into eleven sectors for flexible sector erase
capability. The 8 bits of data appear on I/O0 - I/O7 while the
addresses are input on A1 to A17; the 16 bits of data appear
on I/O0~I/O15. The A29400 is offered in 44-pin SOP and 48-Pin
TSOP packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write or
erase operations. However, the A29400 can also be
programmed in standard EPROM programmers.
The A29400 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it is
in the Erase Suspend. Besides the I/O6 toggle bit, the A29400
has a second toggle bit, I/O2, to indicate whether the addressed
sector is being selected for erase. The A29400 also offers the
ability to program in the Erase Suspend mode. The standard
A29400 offers access times of 55, 70 and 90 ns, allowing high-
speed microprocessors to operate without wait states. To
eliminate bus contention the device has separate chip enable
( CE ), write enable ( WE ) and output enable ( OE ) controls.
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C
- Reliable operation for the life of the system
n Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
n Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
n Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
n Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data
n Package options
- 44-pin SOP or 48-pin TSOP (I)
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29400 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands are
written to the command register using standard microprocessor
write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry.
Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the
device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it is
not already programmed) before executing the erase operation.
During erase, the device automatically times the erase pulse
widths and verifies proper erase margin.
PRELIMINARY (February, 2001, Version 0.1)
1
AMIC Technology, Inc.






A29512A Datasheet, Funktion
A29400 Series
Table 2. A29400 Top Boot Block Sector Address Table
Sector A17
A16
A15
A14
A13
A12
Sector Size Address Range (in hexadecimal)
(Kbytes/Kwords)
(x8)
(x16)
Address Range Address Range
SA0 0 0 0 X X X
64/32
00000h - 0FFFFh 00000h - 07FFFh
SA1 0 0 1 X X X
64/32
10000h - 1FFFFh 08000h - 0FFFFh
SA2 0 1 0 X X X
64/32
20000h - 2FFFFh 10000h - 17FFFh
SA3 0 1 1 X X X
64/32
30000h - 3FFFFh 18000h - 1FFFFh
SA4 1 0 0 X X X
64/32
40000h - 4FFFFh 20000h - 27FFFh
SA5 1 0 1 X X X
64/32
50000h - 5FFFFh 28000h - 2FFFFh
SA6 1 1 0 X X X
64/32
60000h - 6FFFFh 30000h - 37FFFh
SA7 1 1 1 0 X X
32/16
70000h - 77FFFh 38000h - 3BFFFh
SA8 1 1 1 1 0 0
8/4 78000h - 79FFFh 3C000h - 3CFFFh
SA9 1 1 1 1 0 1
8/4 7A000h - 7BFFFh 3D000h - 3DFFFh
SA10
1
1
1
1
1
X
16/8 7C000h - 7FFFFh 3E000h - 3FFFFh
Table 3. A29400 Bottom Boot Block Sector Address Table
Sector A17 A16 A15 A14 A13 A12
SA0 0 0 0 0 0 X
SA1 0 0 0 0 1 0
SA2 0 0 0 0 1 1
SA3 0 0 0 1 X X
SA4 0 0 1 X X X
SA5 0 1 0 X X X
SA6 0 1 1 X X X
SA7 1 0 0 X X X
SA8 1 0 1 X X X
SA9 1 1 0 X X X
SA10
1
1
1
X
X
X
Sector Size
(Kbytes)
16/8
8/4
8/4
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range
(x8) (x16)
Address Range Address Range
00000h - 03FFFh 00000h - 01FFFh
04000h - 05FFFh 02000h - 02FFFh
06000h - 07FFFh 03000h - 03FFFh
08000h - 0FFFFh 04000h - 07FFFh
10000h - 1FFFFh 08000h - 0FFFFh
20000h - 2FFFFh 10000h - 17FFFh
30000h - 3FFFFh 18000h - 1FFFFh
40000h - 4FFFFh 20000h - 27FFFh
50000h - 5FFFFh 28000h - 2FFFFh
60000h - 6FFFFh 30000h - 37FFFh
70000h - 7FFFFh 38000h - 3FFFFh
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is
primarily intended for programming equipment to
automatically match a device to be programmed with its
corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through
the command register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pinA9. Address
pins A6, A1, and A0 must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when
verifying sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown
in the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on
using the autoselect mode.
PRELIMINARY (February, 2001, Version 0.1)
6
AMIC Technology, Inc.

6 Page









A29512A pdf, datenblatt
A29400 Series
Table 5. A29400 Command Definitions
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID,
Top Boot Block
Device ID,
Bottom Boot Block
1
1
Word
Byte
Word
Byte
4
4
Word
Byte 4
Continuation ID
Word 4
Byte
Sector Protect Verify
(Note 9)
Word
Byte
4
Program
Chip Erase
Sector Erase
Erase Suspend (Note 9)
Erase Resume (Note 10)
Word
Byte 4
Word
Byte 6
Word
Byte 6
1
1
First
Second
Addr Data Addr Data
RA RD
XXX F0
555
AAA AA
555
AA
AAA
2AA
55
555
2AA
55
555
555 AA 2AA 55
AAA 555
555 AA
AAA
2AA 55
555
555 2AA
AA
AAA
55
555
555
AAA
555
AAA
555
AAA
XXX
XXX
AA
AA
AA
B0
30
2AA
555 55
2AA
55
555
2AA
555 55
Bus Cycles (Notes 2 - 5)
Third
Fourth
Fifth
Sixth
Addr Data Addr Data Addr Data Addr Data
555
AAA
555
AAA
555
AAA
90
90
90
555 90
AAA
555
90
AAA
555
AAA
555
AAA
555
AAA
A0
80
80
X00 37
X01 B3B0
X02 B0
X01 B331
X02 31
X03
7F
X06
(SA) XX00
X02 XX01
(SA) 00
X04 01
PA PD
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
10
AAA
SA 30
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A17 - A12 select a unique sector.
Note:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operation.
4. Address bits A17 - A11 are don't cares for unlock and command cycles, unless SA or PA required.
5. No unlock or command cycles required when reading array data.
6. The Reset command is required to return to reading array data when device is in the autoselect mode, or if I/O5 goes high
(while the device is providing status data).
7. The fourth cycle of the autoselect command sequence is a read cycle.
8. The data is 00h for an unprotected sector and 01h for a protected sector. See "Autoselect Command Sequence" for more information.
9. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode.
10. The Erase Resume command is valid only during the Erase Suspend mode.
11. The time between each command cycle has to be less than 50µs.
PRELIMINARY (February, 2001, Version 0.1)
12
AMIC Technology, Inc.

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