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A29002T-150 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A29002T-150
Beschreibung 256K X 8 Bit CMOS 5.0 Volt-only/ Boot Sector Flash Memory
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A29002T-150 Datasheet, Funktion
A29002/A290021 Series
256K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Features
n 5.0V ± 10% for read and write operations
n Access times:
- 55/70/90/120/150 (max.)
n Current:
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 µA typical CMOS standby
n Flexible sector architecture
- 16 Kbyte/ 8 KbyteX2/ 32 Kbyte/ 64 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
n Top or bottom boot block configurations available
n Embedded Erase Algorithms
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125°C
- Reliable operation for the life of the system
n Compatible with JEDEC-standards
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
n Data Polling and toggle bits
- Provides a software method of detecting completion
of program or erase operations
n Erase Suspend/Erase Resume
- Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector, then
resumes the erase operation
n Hardware reset pin (RESET )
- Hardware method to reset the device to reading array
data (not available on A290021)
n Package options
- 32-pin P-DIP, PLCC, or TSOP (Forward type)
General Description
The A29002 is a 5.0 volt-only Flash memory organized as
262,144 bytes of 8 bits each. The A29002 offers the RESET
function, but it is not available on A290021. The 256 Kbytes
of data are further divided into seven sectors for flexible
sector erase capability. The 8 bits of data appear on I/O0 -
I/O7 while the addresses are input on A0 to A17. The A29002
is offered in 32-pin PLCC, TSOP, and PDIP packages. This
device is designed to be programmed in-system with the
standard system 5.0 volt VCC supply. Additional 12.0 volt
VPP is not required for in-system write or erase operations.
However, the A29002 can also be programmed in standard
EPROM programmers.
The A29002 has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29002 has a second toggle bit, I/O2, to indicate whether the
addressed sector is being selected for erase. The A29002
also offers the ability to program in the Erase Suspend mode.
The standard A29002 offers access times of 55, 70, 90, 120,
and 150 ns, allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention the device
has separate chip enable ( CE ), write enable ( WE ) and
output enable ( OE ) controls.
The device requires only a single 5.0 volt power supply for both
read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
The A29002 is entirely software command set compatible with
the JEDEC single-power-supply Flash standard. Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as input
to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command
sequence. This initiates the Embedded Erase algorithm - an
internal algorithm that automatically preprograms the array (if it
is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper erase margin.
(February, 2002, Version 1.0)
1 AMIC Technology, Inc.






A29002T-150 Datasheet, Funktion
A29002/A290021 Series
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
Sector
SA0
SA1
SA2
SA3
SA4
SA5
SA6
Table 2. A29002/A290021 Top Boot Block Sector Address Table
A17 A16 A15 A14 A13 Sector Size
(Kbytes)
0 0XXX
64
0 1XXX
64
1 0XXX
64
11 0XX
32
11100
8
11101
8
1111X
16
Address Range
00000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 37FFFh
38000h - 39FFFh
3A000h - 3BFFFh
3C000h - 3FFFFh
Table 3. A29002/A290021 Bottom Boot Block Sector Address Table
A17 A16 A15 A14 A13 Sector Size
(Kbytes)
0000X
16
00010
8
00011
8
00 1XX
32
0 1XXX
64
1 0XXX
64
1 1XXX
64
Address Range
00000h - 03FFFh
04000h - 05FFFh
06000h - 07FFFh
08000h - 0FFFFh
10000h - 1FFFFh
20000h - 2FFFFh
30000h - 3FFFFh
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically
match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes
can also be accessed in-system through the command
register.
When using programming equipment, the autoselect mode
requires VID (11.5V to 12.5 V) on address pinA9. Address
pins A6, A1, and AO must be as shown in Autoselect
Codes (High Voltage Method) table. In addition, when
verifying sector protection, the sector address must appear
on the appropriate highest order address bits. Refer to the
corresponding Sector Address Tables. The Command
Definitions table shows the remaining address bits that are
don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.To access the
autoselect codes in-system, the host system can issue the
autoselect command via the command register, as shown
in the Command Definitions table. This method does not
require VID. See "Command Definitions" for details on
using the autoselect mode.
Table 4. A29002/A290021 Autoselect Codes (High Voltage Method)
Description
Manufacturer ID: AMIC
Device ID: A29002/
A290021
Sector Protection
Verification
A17 - A13 A12 - A10 A9 A8 - A7 A6 A5 - A2 A1
X X VID X VIL X VIL
X
X
VID X VIL X
VIL
Sector
X VID X VIL X VIH
Address
AO Identifier Code on
I/O7 - I/O0
VIL 37h
VIH Top Boot Block: 8Ch
Bottom Boot Block: 0Dh
VIL 01h (protected)
00h (unprotected)
Continuation ID
X X VID X VIL X VIH VIH
7Fh
Note: CE =VIL, OE =VIL and WE =VIH when Autoselect Mode
(February, 2002, Version 1.0)
6 AMIC Technology, Inc.

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A29002T-150 pdf, datenblatt
Write Operation Status
Several bits, I/O2, I/O3, I/O5, I/O6, and I/O7, are provided in
the A29002/A290021 to determine the status of a write
operation. Table 6 and the following subsections describe
the functions of these status bits. I/O7, I/O6 and I/O2 each
offer a method for determining whether a program or erase
operation is complete or in progress. These three bits are
discussed first.
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend.
Data Polling is valid after the rising edge of the final WE
pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device
outputs on I/O7 the complement of the datum programmed
to I/O7. This I/O7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm
is complete, the device outputs the datum programmed to
I/O7. The system must provide the program address to
read valid status information on I/O7. If a program address
falls within a protected sector, Data Polling on I/O7 is
active for approximately 2µs, then the device returns to
reading array data.
During the Embedded Erase algorithm, Data Polling
produces a "0" on I/O7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data Polling produces a "1" on I/O7.This
is analogous to the complement/true datum output
described for the Embedded Program algorithm: the erase
function changes all the bits in a sector to "1"; prior to this,
the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected
for erasure to read valid status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100µs, then the device returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
When the system detects I/O7 has changed from the
complement to true data, it can read valid data at I/O7 - I/O0
on the following read cycles. This is because I/O7 may
change asynchronously with I/O0 - I/O6 while Output Enable
( OE ) is asserted low. The Data Polling Timings (During
Embedded Algorithms) figure in the "AC Characteristics"
section illustrates this. Table 6 shows the outputs for Data
Polling on I/O7. Figure 4 shows the Data Polling algorithm.
A29002/A290021 Series
START
Read I/O7-I/O0
Address = VA
I/O7 = Data ?
Yes
No
No
I/O5 = 1?
Yes
Read I/O7 - I/O0
Address = VA
I/O7 = Data ?
Yes
No
FAIL
PASS
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O7 should be rechecked even if I/O5 = "1" because
I/O7 may change simultaneously with I/O5.
Figure 4. Data Polling Algorithm
(February, 2002, Version 1.0)
12 AMIC Technology, Inc.

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