|
|
PDF A28F010 Data sheet ( Hoja de datos )
| Número de pieza | A28F010 | |
| Descripción | 1024K (128K x 8) CMOS FLASH MEMORY | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de A28F010 (archivo pdf) en la parte inferior de esta página. Total 23 Páginas | ||
|
No Preview Available !
A28F010
1024K (128K x 8) CMOS FLASH MEMORY
(Automotive)
Y Automotive Temperature Range
b40 C to a125 C
Y Flash Memory Electrical Chip-Erase
1 Second Typical Chip-Erase
Y Quick-Pulse Programming Algorithm
10 ms Typical Byte-Program
2 Second Chip-Program
Y 1 000 Erase Program Cycles Minimum
over Automotive Temperature Range
Y 12 0V g5% VPP
Y High-Performance Read
120 ns Maximum Access Time
Y CMOS Low Power Consumption
30 mA Maximum Active Current
300 mA Maximum Standby Current
Y Integrated Program Erase Stop Timer
Y Command Register Architecture for
Microprocessor Microcontroller
Compatible Write Interface
Y Noise Immunity Features
g10% VCC Tolerance
Maximum Latch-Up Immunity
through EPI Processing
Y ETOXTM III Flash Nonvolatile Memory
Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y JEDEC-Standard Pinouts
32-Pin Plastic DIP
32-Lead PLCC
(See Packaging Spec Order 231369)
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read write
random access nonvolatile memory The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology Memory contents can be rewritten in a test socket in a PROM-programmer socket on-
board during subassembly test in-system during final test and in-system after-sale The 28F010 increases
memory flexibility while contributing to time- and cost-savings
The 28F010 is a 1024-kilobit nonvolatile memory organized as 131 072 bytes of 8 bits Intel’s 28F010 is
offered in 32-pin Plastic DIP or 32-lead PLCC packages Pin assignments conform to JEDEC standards
Extended erase and program cycling capability is designed into Intel’s ETOXTM III (EPROM Tunnel Oxide)
process technology Advanced oxide processing an optimized tunneling structure and lower electric field
combine to extend reliable cycling beyond that of traditional EEPROMs With the 12 0V VPP supply the
28F010 performs a minimum of 1 000 erase and program cycles well within the time limits of the Quick-Pulse
Programming and Quick-Erase algorithms
Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds low
power consumption and immunity to noise Its 120 nanosecond access time provides no-WAIT-state perform-
ance for a wide range of microprocessors and microcontrollers Maximum standby current of 300 mA trans-
lates into power savings when the device is deselected Finally the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins from b1V to VCC a 1V
With Intel’s ETOX III process base the 28F010 leverages years of EPROM experience to yield the highest
levels of quality reliability and cost-effectiveness
In order to meet the rigorous environmental requirements of automotive applications Intel offers the 28F010 in
extended automotive temperature range Read and write characteristics are guaranteed over the range of
b40 C to a125 C ambient
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290266-004
1 page  
A28F010
Figure 3 28F010 in a 80C186 System
290266 – 4
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming The
28F010 introduces a command register to manage
this new functionality The command register allows
for 100% TTL-level control inputs fixed power sup-
plies during erasure and programming and maxi-
mum EPROM compatibility
In the absence of high voltage on the VPP pin the
28F010 is a read-only memory Manipulation of the
external memory-control pins yields the standard
EPROM read standby output disable and Intelli-
gent Identifier operations
The same EPROM read standby and output disable
operations are available when high voltage is ap-
plied to the VPP pin In addition high voltage on VPP
enables erasure and programming of the device All
functions associated with altering memory con-
tents Intelligent Identifier erase erase verify pro-
gram and program verify are accessed via the
command register
Commands are written to the register using standard
microprocessor write timings Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry Write
cycles also internally latch addresses and data
needed for programming or erase operations With
the appropriate command written to the register
standard microprocessor read timings output array
data access the Intelligent Identifier codes or out-
put data for erase and program verification
Integrated Program Erase Stop Timer
Successive command write cycles define the dura-
tions of program and erase operations specifically
the program or erase time durations are normally
terminated by associated program or erase verify
commands An integrated stop timer provides simpli-
fied timing control over these operations thus elimi-
nating the need for maximum program erase timing
specifications Program and erase pulse durations
are minimums only When the stop timer terminates
a program or erase operation the device enters an
inactive state and remains inactive until receiving the
appropriate verify or reset command
Write Protection
The command register is only alterable when VPP is
at high voltage Depending upon the application the
system designer may choose to make the VPP pow-
er supply switchable available only when memory
updates are desired When high voltage is removed
5
5 Page 
A28F010
Bus
Operation
Command
Comments
Entire Memory Must e 00H
Before Erasure
Standby
Use Quick-Pulse
Programming Algorithm
(Figure 4)
Wait for VPP Ramp to VPPH(1)
Write
Write
Set-up
Erase
Erase
Initialize Addresses and
Pulse-Count
Data e 20H
Data e 20H
Standby
Write
Standby
Read
Erase(3)
Verify
Duration of Erase Operation
(tWHWH2)
Addr e Byte to Verify
Data e A0H Stops Erase
Operation(2)
tWHGL
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Read
Standby
Data e 00H Resets the
Register for Read Operations
Wait for VPP Ramp to VPPL(1)
290266 – 6
NOTES
1 See DC Characteristics for value of VPPH The VPP
power supply can be hard-wired to the device or
switchable When VPP is switched VPPL may be
ground no-connect with a resistor tied to ground or
less than 6 5V Refer to Principles of Operation
2 Refer to Principles of Operation
3 Erase Verify is performed only after chip-erasure A
final read compare may be performed (optional) after
the register is written with the read command
4 CAUTION The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the de-
vice
Figure 5 A28F010 Quick-Erase Algorithm
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet A28F010.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| A28F010 | 1024K (128K x 8) CMOS FLASH MEMORY | Intel Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |