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ACT-5260PC-150F24T Schematic ( PDF Datasheet ) - Aeroflex Circuit Technology

Teilenummer ACT-5260PC-150F24T
Beschreibung ACT5260 64-Bit Superscaler Microprocessor
Hersteller Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology Logo 




Gesamt 8 Seiten
ACT-5260PC-150F24T Datasheet, Funktion
ACT5260
64-Bit Superscaler Microprocessor
Features
s Full militarized QED RM5260 microprocessor
s Dual Issue superscalar QED RISCMark- can issue one
integer and one floating-point instruction per cycle
microprocessor - can issue one integer and one
floating-point instruction per cycle
q 100, 133 and 150MHz frequency (200MHz future option)
Consult Factory for latest speeds
q 260 Dhrystone2.1 MIPS
q SPECInt95 4.8. SPECfp95 5.1
s High performance system interface compatible with R4600,
R4700 and R5000
q 64-bit multiplexed system address/data bus for optimum
price/performance up to 100 MHz operating frequency
q High performance write protocols maximize uncached
write bandwidth
q Operates at input system clock multipliers of 2 through 8
q 5V tolerant I/O's
q IEEE 1149.1 JTAG boundary scan
s Integrated on-chip caches - up to 3.2GBps internal data rate
q 16KB instruction - 2 way set associative
q 16KB data - 2 way set associative
q Virtually indexed, physically tagged
q Write-back and write-through on per page basis
q Pipeline restart on first double for data cache misses
s Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)
q 48 dual entries map 96 pages
q Variable page size (4KB to 16MB in 4x increments)
s Embedded supply de-coupling capacitors and Pll filter
components
s High-performance floating point unit - up to 400 MFLOPS
q Single cycle repeat rate for common single precision
operations and some double precision operations
q Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
q Single cycle repeat rate for single precision combined
multiply-add operation
s MIPS IV instruction set
q Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
q Conditional moves to reduce branch frequency
q Index address modes (register + register)
s Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
q I and D cache locking by set
q Optional dedicated exception vector for interrupts
s Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction
q 5 Watts typical at 3.3V, less than 175 mwatts in Standby
s 208-lead CQFP, cavity-up package (F17)
s 208-lead CQFP, inverted footprint (F24), Intended to duplicate
the commercial QED footprint (Consult Factory)
s 179-pin PGA package (Future Product) (P10)
BLOCK DIAGRAM
Data Set A
Store Buffer
Phase Lock Loop
Data Tag A
DTLB Physical
Data Tag B
Sys AD
Instruction Set A
Instruction Select
Write Buffer
Read Buffer
Data Set B
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Integer Instruction Register
FP Instruction Register
Instruction Set B
Control
DBus
Floating-point
Register File
Unpacker/Packer
Floating-point
MAdd, Add, Sub,Cvt
Div, SqRt
FPIBus
Tag Aux Tag
Joint TLB
Coprocessor 0
System/Memory
Control
DVA
IVA
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
IntIBus
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
ABus
Integer Multiply, Divide
eroflex Circuit Technology – RISC TurboEngines For The Future © SCD5260 REV A 3/29/99






ACT-5260PC-150F24T Datasheet, Funktion
Package Information – "F17" – CQFP 208 Leads
1.131 (28.727) SQ
1.109 (28.169) SQ
53
52
104
105
1.009 (25.63)
.9998 (25.37)
51 Spaces at .0197
(51 Spaces at .50)
1
Pin 1 Chamfer
208
Detail "A"
.960 (24.384) SQ
REF
.010R MIN
.010R MIN
.015 (.381)
.009 (.229)
0°±5°
.130 (3.302)
MAX
.100 (2.540)
.080 (2.032)
.035 (.889)
.025 (.635)
.009 (.253)
.007 (.178)
Detail "A"
156
157
.055 (1.397)
REF
.115 (2.921)
MAX
1.331 (33.807)
1.269 (32.233)
.055 (1.397)
.045 (1.143)
Units: Inches (Millimeters)
Note: Pin rotation is opposite of QEDs PQUAD due to cavity-up construction.
Future Package – "P10" – PGA 179 Pins (Advanced)
Bottom View
Side View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
V
U
T
R
P
N
M
L
K 1.700 1.840
J BSC 1.880
H
G
F
E
D
C
B
A
1.700
BSC
Aeroflex Circuit Technology
1.840
1.880
6
.100
BSC
.018
.050
.221
MAX
SCD5260 REV A 3/29/99 Plainview NY (516) 694-6700

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