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PDF ACS8515P Data sheet ( Hoja de datos )
| Número de pieza | ACS8515P | |
| Descripción | Line Card Protection Switch for SONET or SDH Network Elements | |
| Fabricantes | Semtech Corporation | |
| Logotipo |  |
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ADVANCED COMMUNCIATIONS
ACS8515 LC/P
Line Card Protection Switch
for SONET or SDH Network Elements
FINAL
Description
The ACS8515 is a highly integrated, single-chip
solution for hit-less protection switching of SEC
clocks from Master and Slave SETS clockcards
in a SONET or SDH Network Element. The
ACS8515 has fast activity monitors on the in-
puts and will implement automatic system pro-
tection switching against master clock failure. A
further input is provided for an optional standby
SEC clock. The ACS8515 is fully compliant with
the required specifications and standards.
The ACS8515 can perform frequency translation
from a SEC input clock distributed along a back
plane to a different local line card clock, e.g. 8
kHz distributed on the back plane and 19.44 MHz
generated on the line cards.
An SPI serial port is incorporated, providing ac-
cess to the configuration and status registers for
device setup.
The ACS8515 can utilise either a low cost XO
oscillator module, or a TCXO with full tempera-
ture calibration - as required by the application.
Block Diagram
Features
Suitable for Stratum 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia
specifications
Three SEC input clocks, from 2 kHz to 155.52
MHz
Generates two SEC output clocks, up to 311.04
MHz
Frequency translation of SEC input clock to a
different local line card clock
Robust input clock source frequency and
activity monitoring on all inputs
Supports Free-Run, Locked and Holdover
modes of operation
Automatic hit-less source switchover on loss
of input
External force fast switch between SEC inputs
Phase build-out for output clock phase
continuity during input switchover
SPI compatible serial microprocessor interface
Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
Single 3.3 v operation. 5 v I/O compatible
Operating temperature (ambient) -40°C to
+85°C
Available in 64 pin LQFP package
3 x SEC Input
M a s te r/Slav e
+ Standby:
N x 8kHz
1. 54 4M H z
2. 04 8M H z
6.48M Hz
19 .4 4M H z
38 .8 8M H z
51 .8 4M H z
77 .7 6M H z
15 5. 5 2M H z
P lu s :
M FrSy n c
3xSEC
Inp ut
Ports
Monitors
MFrSync
DP LL
Frequency Synthesis
APLL
Frequency
Dividers
Chip C lock
Ge nera tor
P riorit y
T able
Re gis ter
Set
SPI Compatible Serial
M icroprocessor Port
2xSEC
O utp ut
Ports
FrSync
MFrSync
2 x SEC Output
in clu d in g :
1. 54 4/2 .0 4 8M H z
3. 08 8/4 .0 9 6M H z
6. 17 6/8 .1 9 2M H z
12 .3 5 2/ 1 6. 38 4M H z
19 .4 4M H z
38 .8 8M H z
15 5. 5 2M H z
31 1. 0 4M H z
Plu s :
2kHz MFrSync
8kHz FrSync
TCXO or XO
Revision 2.05/Jan 2001 ã2001 Semtech Corp
www.semtech.com
1 page  
ACS8515 LC/P
ADVANCED COMMUNCIATIONS
Others
FINAL
PIN
SYMBOL
IO TYPE
NAME/DESCRIPTION
5
INTREQ
O
- Interupt request: Software Interrupt enable
6
REFCLK
I
TTL
Reference clock: 12.8 MHz (refer to section headed Local
Oscillator Clock)
13
SRCSW
I TTLD Source switching: Force fast source switching on SEC1 and SEC2
17
FrSync
O
TTL
Output reference: 8 kHz Frame Sync, 50:50 mark/space ratio
output
18
MFrSync
O
TTL
Output reference: 2 kHz Multi-Frame Sync, 50:50 mark/space
ratio output
19
20
O1POS
O1NEG
O
LVDS/
PECL
Output reference: Programmable, default 38.88 MHz LVDS
23
24
SEC1_POS
SEC1_NEG
I
LVDS/
PECL
Input reference: Programmable, default 19.44 MHz LVDS
25
26
SEC2_POS
SEC2_NEG
I
PECL/
LVDS
Input reference: Programmable, default 19.44 MHz PECL
28
Sync2k
I TTLD Multi-Frame Sync 2 kHz: Multi-Frame Sync input
29
SEC1
I TTLD Input reference: Programmable, default 8 kHz
30
SEC2
I TTLD Input reference: Programmable, default 8 kHz
33
IC
-
-
Internally connected: Connect to GND. Reserved for Slave Multi-
frame sync 2 kHz input on next revision.
34
SEC3
I
TTLD
Input reference: External standby reference clock source,
programmable, default 19.44 MHz
35
IC
-
-
Internally connected: Connect to GND. Reserved for external
standby 2 kHz Multi-frame sync input on next revision.
42
CLKE
I
TTLD
SCLK edge select: SCLK active edge select, CLKE=1 selects
falling edge of SCLK to be active
43 SDI I TTLD Microprocessor interface address: Serial data input
44
CSB
I
TTLU
Chip select (active low): This pin is asserted Low by the
microprocessor to enable the microprocessor interface
Address Latch Enable: default Serial data clock. When this pin
47
SCLK
I TTLD transitions from high to low, the address bus inputs are latched
into the internal registers
48
PORB
I
TTLU
Power on reset: Master reset. If PORB is forced Low, all internal
states are reset back to default values
Note: I = input, O = output, P = power, TTLU = TTL input with pull-up resistor, TTLD = TTL input with pull-down resistor
Revision 2.05/Jan 2001 ã2001 Semtech Corp
5
www.semtech.com
5 Page 
ADVANCED COMMUNCIATIONS
ACS8515 LC/P
FINAL
3HDNWRSHDN MLWWHU DQG ZDQGHU DPSOLWXGH ORJ
VFDOH
$
$
-LWWHU DQG ZDQGHU IUHTXHQF\ ORJ VFDOH
I I I
I
Figure 2: Minimum Input Jitter Tolerance for inputs supporting G.703 compliant sources
Ty p e
Spec.
DS1
E1
GR-1244-CORE
ITU G.823
Amplitude
(UI pk-pk)
Freq u en cy
(Hz)
A1
A2 F1 F2
F3
F4
5
0.1 10 500 8k
40k
1.5 0.2 20 2.4k 18k 100k
Table 4: Amplitude and Frequency values for Jitter Tolerance for inputs supporting G.703 compliant sources
Low-speed Output Clock
Frame Sync and Multi-Frame Sync Clocks
The O2 SEC clock is supplied on a TTL port with
a fixed frequency of 19.44 MHz.
High-speed Output Clock
The O1 SEC clock is supplied on a PECL/LVDS
port with spot frequencies of 19.44 MHz, 38.88
MHz, 155.52 MHz, 311.04 MHz and Dig 1
(where Dig 1 is 1.544/2.048 MHz and multiples
of 2, 4 and 8 depending on SONET/SDH mode
setting). The actual frequency is selectable via
the cnfg_differential_outputs register. The O1
port can also support 311.04 MHz, which is
enabled via the cnfg_T0_output_enable
register. The O1 port can be made LVDS or
PECL compatible via the
cnfg_differential_outputs register.
Frame Sync (8 kHz) and Multi-Frame Sync (2
kHz) clocks will be provided on outputs FrSync
and MFrSync. The FrSync and MFrSync clocks
have a 50:50 mark space ratio.
Output Wander and Jitter
Wander and jitter present on the output clocks
are dependent on:
The magnitude of wander and jitter on the selected
input reference clock (in locked mode);
The internal wander and jitter transfer characteristic
(in locked mode);
The jitter on the local oscillator clock;
The wander on the local oscillator clock (in Hold-Over
mode).
Revision 2.05/Jan 2001 ã2001 Semtech Corp
11
www.semtech.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ACS8515P.PDF ] | |
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