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PDF ACS8510 Data sheet ( Hoja de datos )
| Número de pieza | ACS8510 | |
| Descripción | Synchronous Equipment Timing Source for SONET or SDH Network Elements | |
| Fabricantes | Semtech Corporation | |
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ADVANCED COMMUNCIATIONS
ACS8510 SETS
Synchronous Equipment Timing Source
for SONET or SDH Network Elements
FINAL
Description
The ACS8510 is a highly integrated, single-chip
solution for the Synchronous Equipment Timing
Source (SETS) function in a SONET or SDH Net-
work Element. The device generates SONET or
SDH Equipment Clocks (SEC) and frame synchro-
nization clocks. The ACS8510 is fully compliant
with the required specifications and standards.
The device supports Free-Run, Locked and
Holdover modes. It also supports all three types
of reference clock source: recovered line clock,
PDH network, and node synchronization. The
ACS8510 generates independent SEC and BITS
clocks, an 8 kHz Frame Synchronization clock
and a 2 kHz Multi-Frame Synchronization clock.
Two ACS8510 devices can be used together in a
Master/Slave configuration mode allowing sys-
tem protection against a single ACS8510 failure.
A microprocessor port is incorporated, providing
access to the configuration and status registers
for device setup and monitoring. The ACS8510
supports IEEE 1149.1 JTAG boundary scan.
* Meets Holdover requirements, lowest bandwidth 0.1 Hz.
Block Diagram
Features
Suitable for Stratum 3E*, 3, 4E and 4 SONET
or SDH Equipment Clock (SEC) applications
Meets AT&T, ITU-T, ETSI and Telcordia specifi-
cations
Accepts 14 individual input reference clocks
Generates 11 output clocks
Supports Free-Run, Locked and Holdover
modes of operation
Robust input clock source quality monitoring on
all inputs
Automatic hit-less source switchover on loss
of input
Phase build-out for output clock phase conti-
nuity during input switchover and mode transi-
tions
Microprocessor interface - Intel, Motorola,
Serial, Multiplexed, EEPROM
Programmable wander and jitter tracking/
attenuation 0.1 Hz to 20 Hz
Support for Master/Slave device configuration
alignment and hot/standby redundancy
IEEE 1149.1 JTAG Boundary Scan
Single 3.3 v operation. 5 v I/O compatible
Operating temperature (ambient) -40°C to
+85°C
Available in 100 pin LQFP package
14 Inp ut
Referenc e
Source
includin g:
AM I 64/8 kHz
2 kHz
8 kHz
N x 8 kHz
1.544 MHz
2.048 MHz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
Inp ut
Ports
6xTIN1
4xTIN2
4xTIN3
MFrSync
T CK
TDI IEEE
TMS 1149.1
T RST
TDO JTAG
TOUT4
se lec tor
Monitors
Div ider
Dig ital
PFD Loop
Filter
DPLL/F req. Synthesis
DTO
TO UT 0
se lec tor
Div ider
Dig ital
PFD Loop DTO
Filter
DPLL/Freq. S ynthesis
Chip C lock
Ge nera tor
P riorit y
T able
Re gis ter
Set
Micropro cessor
Port
TCXO (*OCXO)
CLK
Revision 2.07/Jan 2001 ã2001 Semtech Corp
A PLL
Frequency
Dividers
O utp ut
Ports
2xT O UT 4
7xT O UT 0
MFrSync
FrSync
11 Outp ut Ports
includin g:
1.544/2.048 M Hz
3.088/4.096 M Hz
6.176/8.182 M Hz
12.352/16.384 M Hz
6.48 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
AM I 64/8 kHz
2 kHz MFrSy nc
8 kHz FrSy nc
www.semtech.com
1 page  
ACS8510 SETS
ADVANCED COMMUNCIATIONS
Others
FINAL
PIN
SYMBOL
IO TYPE
NAME/DESCRIPTION
JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary
2
TRST
I TTLD Scan mode. TRST = 0 for normal device operation (JTAG logic
transparent). If not used connect to GND or leave floating.
7
TMS
I
TTLU
JTAG Test Mode Select: Boundary Scan enable. Sampled on
rising edge of TCK. If not used connect to VDD or leave floating.
8
INTREQ
O
TTL
CMOS
Interrupt Request: Active high software Interrupt output
JTAG Clock: Boundary Scan clock input. If not used connect to
GND or leave floating. This pin may require a capacitor placed
9 TCK I TTLD between the pin and the nearest GND, to reduce noise pickup. A
value of 10 pF should be adequate, but the value is dependent on
PCB layout.
10
REFCLK
I
TTL
Reference Clock: 12.8 MHz (refer to section headed Local
Oscillator Clock)
18
SRCSW
I TTLD Source Switching: Force Fast Source Switching
21
TDO
O
TTL JTAG Output: Serial test data output. Updated on falling edge of
CMOS TCK. If not used leave floating.
23
TDI
I
TTLU
JTAG Input: Serial test data Input. Sampled on rising edge of TCK.
If not used connect to VDD or leave floating.
24 I1 I AMI Input reference 1: composite clock 64 kHz + 8 kHz
25 I2 I AMI Input reference 2: composite clock 64 kHz + 8 kHz
27
TO8NEG
O
AMI
Output reference 8: composite clock, 64 kHz + 8 kHz negative
pulse
28
TO8POS
O
AMI
Output reference 8: composite clock, 64 kHz + 8 kHz positive
pulse
30
FrSync
O
TTL Output reference 10: 8 kHz Frame Sync clock output (square
CMOS wave)
31
MFrSync
O
TTL Output reference 11: 2 kHz Multi-Frame Sync clock output
CMOS (square wave)
34
35
TO6POS
TO6NEG
O
PECL/
LVDS
Output reference 6: default 38.88 MHz. Also Dig1 (1.544
MHz/2.048 MHz and 2, 4, 8 x), 19.44 MHz, 155.52 MHz, 311.04
MHz. Default type LVDS.
36
37
TO7POS
TO7NEG
O
LVDS/ Output reference 7: default 19.44 MHz. Also 51.84 MHz, 77.76
PECL MHz, 155.52 MHz. Default type PECL.
40
41
I5POS
I5NEG
I
LVDS
PECL
Input reference 5: default 19.44 MHz, default type LVDS
42
43
I6POS
I6NEG
I
PECL
LVDS
Input reference 6: default 19.44 MHz, default type PECL
Revision 2.07/Jan 2001 ã2001 Semtech Corp
5
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5 Page 
ACS8510 SETS
ADVANCED COMMUNCIATIONS
FINAL
Notes for Table 1.
Note 1: TTL ports (compatible also with CMOS signals) support clock speeds up to 100 MHz, with the highest spot
frequency being 77.76 MHz. The actual spot frequencies are: 2 kHz, 4 kHz, 8 kHz, 1.544 MHz/2.048 MHz, 6.48 MHz,
19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. There are different output clock frequencies available
for SONET and SDH applications. SONSDHB controls the default frequency output. F1/F2 means that the output
frequency is F1 when the SONSDHB pin is High and F2 when SONSDHB pin is Low.
Note 2: PECL and LVDS ports support the spot clock frequencies listed above plus 155.52 MHz and 311.04 MHz.
Note 3: Input port <I_11> is set at 12 on the Master SETS IC and 1 on the Slave SETS IC, as default on power up (or
PORB). The default setup of Master or Slave <I_11> priority is determined by the MSTSLVB pin.
DivN examples
To lock to 2.000 MHz.
(1) The cnfg_ref_source_frequency register is set to 11XX0001 (binary) to set the DivN, lock8k bits, and the
frequency to E1/T1. (XX = leaky bucket ID for this input).
(2) The cnfg_mode register (34Hex) bit 2 needs to be set to 1 to select SONET frequencies (T1).
(3) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(4) the DivN register is set to F9 Hex (249 decimal).
To lock to 10.000 MHz.
(1) The cnfg_ref_source_frequency register is set to 11XX0010 (binary) to set the DivN, lock8k bits, and the
frequency to 6.48 MHz. (XX = leaky bucket ID for this input).
(2) The frequency monitors are disabled in cnfg_monitors register (48Hex) by writing 00 to bits 0 and 1.
(3) the DivN register is set to 4E1 Hex (1249 decimal).
An AMI port supports a composite clock,
consisting of a 64 kHz AMI clock with 8 kHz
boundaries marked by deliberate violations of
the AMI coding rules, as specified in ITU
recommendation G.703. Departures from the
nominal pattern are detected within the
ACS8510, and may cause reference-switching
if too frequent. See Figure 9 for more details.
Input Wander and Jitter Tolerance
The ACS8510 is compliant to the requirements
of all relevant standards, principally ITU
Recommendation G.825, ANSI T1.101-1994
and ETS 300 462-5 (1997).
All reference clock inputs have a tight frequency
tolerance but a generous jitter tolerance. Pull-
in, hold-in and pull-out ranges are specified for
each input port in Table 2. Minimum jitter
tolerance masks are specified in Figures 1 and
2, and Tables 3 and 4, respectively. The
ACS8510 will tolerate wander and jitter
components greater than those shown in Figure
1 and Figure 2, up to a limit determined by a
combination of the apparent long-term
frequency offset caused by wander and the
eye-closure caused by jitter (the input source
will be rejected if the offset pushes the
frequency outside the hold-in range for long
enough to be detected, whilst the signal will
also be rejected if the eye closes sufficiently to
affect the signal purity). The 8klocking mode
should be engaged for high jitter tolerance
according to these masks. All reference clock
Revision 2.07/Jan 2001 ã2001 Semtech Corp
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ACS8510.PDF ] | |
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