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ACS373DMSR Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ACS373DMSR
Beschreibung Radiation Hardened Octal Transparent Latch/ Three-State
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 10 Seiten
ACS373DMSR Datasheet, Funktion
ACS373MS
April 1995
Radiation Hardened
Octal Transparent Latch, Three-State
Features
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose 300K RAD (Si)
• Single Event Upset (SEU) Immunity
<1 x 10-10 Errors/Bit-Day (Typ)
• SEU LET Threshold >80 MEV-cm2/mg
• Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range: -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
• Input Current 1µA at VOL, VOH
Description
The Intersil ACS373MS is a radiation hardened octal transparent
latch with three-state outputs. The outputs are transparent to the
inputs when the latch enable (LE) is high. When the LE goes low,
the data is latched. When the Output Enable (OE) is high, the
outputs are in the high impedance state. The latch operation is
independent of the state of the output enable.
The ACS373MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family.
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR, CDIP2-T20, LEAD FINISH C
TOP VIEW
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 LE
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR, CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
Ordering Information
PART NUMBER
ACS373DMSR
ACS373KMSR
ACS373D/Sample
ACS373K/Sample
ACS373HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
+25oC
+25oC
+25oC
SCREENING LEVEL
Intersil Class S Equivalent
Intersil Class S Equivalent
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
Truth Table
OE LE
D
Q
L HHH
LHL L
LL I L
L L hH
HXXZ
NOTE:
L = Low Voltage Level
H = High Voltage Level
X = Don’t Care
Z = High Impedance State
I = Low voltage level one set-up time prior to the high to low latch enable transition
h = High voltage level one set-up time prior to the high to low latch enable transition
Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
D
LATCH
DQ
COMMON
CONTROLS
LE
LE
(11)
OE
(1)
OE
Q
(2, 5, 6, 9, 12,
15, 16, 19)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518799
File Number 3999






ACS373DMSR Datasheet, Funktion
Specifications ACS373MS
Intersil - Space Products MS Screening
Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM)
Radiation Verification (Each Wafer) Method 1019,
4 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull Method 2023
100% Internal Visual Inspection Method 2010
100% Temperature Cycling Method 1010 Condition C
(-65o to +150oC)
100% Constant Acceleration
100% PIND Testing
100% External Visual Inspection
100% Serialization
100% Initial Electrical Test
100% Static Burn-In 1 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 1 (Note 1)
100% Static Burn-In 2 Method 1015, 24 Hours at +125oC Min
100% Interim Electrical Test 2 (Note 1)
100% Dynamic Burn-In Method 1015, 240 Hours at +125oC
or 180 Hours at +135oC
100% Interim Electrical Test 3 (Note 1)
100% Final Electrical Test
100% Fine and Gross Seal Method 1014
100% Radiographics Method 2012 (2 Views)
100% External Visual Method 2009
Group A (All Tests) Method 5005 (Class S)
Group B (Optional) Method 5005 (Class S) (Note 2)
Group D (Optional) Method 5005 (Class S) (Note 2)
CSI and/or GSI (Optional) (Note 2)
Data Package Generation (Note 3)
NOTES:
1. Failures from interim electrical tests 1 and 2 are combined for determining PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures com-
bined, PDA = 3% for subgroup 7 failures). Interim electrical tests 3 PDA (PDA = 5% for subgroups 1, 7, 9 and delta failures combined,
PDA = 3% for subgroup 7 failures).
2. These steps are optional, and should be listed on the purchase order if required.
3. Data Package Contents:
Cover Sheet (P.O. Number, Customer Number, Lot Date Code, Intersil Number, Lot Number, Quantity).
Certificate of Conformance (as found on shipper).
Lot Serial Number Sheet (Good Unit(s) Serial Number and Lot Number).
Variables Data (All Read, Record, and delta operations).
Group A Attributes Data Summary.
Wafer Lot Acceptance Report (Method 5007) to include reproductions of SEM photos. NOTE: SEM photos to include percent of step coverage.
X-Ray Report and Film, including penetrometer measurements.
GAMMA Radiation Report with initial shipment of devices from the same wafer lot; containing a Cover Page, Disposition, RAD Dose,
Lot Number, Test Package, Spec Number(s), Test Equipment, etc. Irradiation Read and Record data will be on file at Intersil.
Propagation Delay Timing Diagram and Load Circuit
VIH
VSS
VOH
VOL
VS INPUT
TPLH
VS
TPHL
OUTPUT
DUT
CL
50pF
TEST
POINT
RL
500
AC VOLTAGE LEVELS
PARAMETER
ACS
VCC
4.50
VIH 4.50
VS 2.25
VIL 0
GND
0
UNITS
V
V
V
V
V
Spec Number 518799
6

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