PDF ACS302-5T3 Data sheet ( Hoja de datos )

Número de pieza	ACS302-5T3
Descripción	THREE LINES AC SWITCH ARRAY
Fabricantes	STMicroelectronics
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No Preview Available ! ® ACS302-5T3 ASD™ AC Switch Family THREE LINES AC SWITCH ARRAY MAIN APPLICATIONS s AC on-off static switching in appliance & industrial control systems s Drive of low power high inductive or resistive loads like: - relay, valve, solenoid, dispenser - pump, fan, micro-motor - low power lamp bulb, door lock FEATURES s THREE HIGH VOLTAGE AC SWITCH ARRAY s BLOCKING VOLTAGE: VDRM / VRRM = 500V s CLAMPING VOLTAGE: VCL = 600 V s NOMINAL CONDUCTING CURRENT PER LINE: IT(RMS) = 0.2 A s NOMINAL CONDUCTING CURRENT FOR TOTAL ARRAY: IT(RMS) = 0.4 A s GATE TRIGGERING CURRENT: IGT < 5 mA BENEFITS s Needs no external overvoltage protection s Enables equipment to meet IEC61000-4-5 standard s Interfaces directly with a microcontroller s Eliminates any stressing gate kick back on the microcontroller s Array structure: design simplified, increase reliability and space saving aspects s Mounting in SO-20 package enables the device to meet IEC335-1 standard PIN-OUT SO-20 Wired package 11.2cm = 2.54’’ OUTPUT 1 1 2 3 4 OUTPUT 2 5 6 7 8 OUTPUT 3 9 10 8.5cm 20 19 18 17 16 15 14 13 12 11 COM GATE 1 GATE 2 3.81cm = 1.5’’ GATE 3 2.54cm = 1’’ COM Pin 11 Pin 1 Pins 2, 3, 4, 6, 7, 8, 10, and 19, 17, 15, 14, 12 are not connected. DESCRIPTION The ACS302 belongs to the AC line switch family built around the ASD™ concept. This high performance device inludes 3 bidirectionnal AC switches able to control an 0.2A resistive or inductive load device. Each ACS™ switch embeds a high voltage clamping structure to absorb the inductive turn off energy and a gate level shifter driver to separate the digital controller from the main switch. It is triggered with a negative gate current flowing out of the gate pin. FUNCTIONAL DIAGRAM OUT1 ACS302 OUT2 S1 S2 COM G1 OUT3 S3 G2 G3 ASD and ACS are trademarks of STMicroelectronics. January 2003 - Ed: 2 1/8 1 page ACS302-5T3 Fig. 5: Maximum power dissipation versus RMS on-state current (per switch). P(W) 0.20 0.18 α = 180° 0.16 0.14 0.12 0.10 0.08 0.06 180° 0.04 α α 0.02 IT(RMS)(A) 0.00 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 Fig. 6: RMS on-state current versus ambient temperature. IT(RMS)(A) 0.45 0.40 3 switches ON 0.35 0.30 0.25 0.20 1 switch ON 0.15 0.10 0.05 0.00 0 Tamb(°C) 25 50 75 α = 180° 100 125 Fig. 7: Relative variation of thermal impedance junction to ambient versus pulse duration . K=[Zth(j-a) / Rth(j-a)] 1.E+00 1.E-01 1.E-02 1 cell 3 cells 1.E-03 1.E-04 1.E-03 1.E-02 tp(s) 1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 Fig. 8: Relative variation of gate trigger current versus junction temperature (typical value). IGT [Tj] / IGT [Tj=25°C] 3.0 2.5 2.0 1.5 1.0 0.5 Tj(°C) 0.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Fig. 9: Relative variation of holding and latching current versus junction temperature (typical values). IL,IH [Tj] / IL,IH [Tj=25°C] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 Tj(°C) 0.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Fig. 10: Surge peak on-state current versus number of cycles. ITSM(A) 8 7 6 5 4 3 Tamb=25°C Repetitive 2 1 0 1 Tj initial=25°C Non repetitive Number of cycles 10 100 t=20ms One cycle 1000 5/8 5 Page

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