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PDF ACF2101 Data sheet ( Hoja de datos )
| Número de pieza | ACF2101 | |
| Descripción | SWITCHED INTEGRATOR | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ACF2101
FPO
Low Noise, Dual
SWITCHED INTEGRATOR
FEATURES
q INCLUDES INTEGRATION CAPACITOR,
RESET AND HOLD SWITCHES, AND
OUTPUT MULTIPLEXER
q LOW NOISE: 10µVrms
q LOW CHARGE TRANSFER: 0.1pC
q WIDE DYNAMIC RANGE: 120dB
q LOW BIAS CURRENT: 100fA
APPLICATIONS
q CURRENT TO VOLTAGE CONVERSION
q PHOTODIODE INTEGRATOR
q CURRENT MEASUREMENT
q CHARGE MEASUREMENT
q CT SCANNER FRONT END
q MEDICAL, SCIENTIFIC, AND INDUSTRIAL
INSTRUMENTATION
DESCRIPTION
The ACF2101 is a dual switched integrator for preci-
sion applications. Each channel can convert an input
current to an output voltage by integration, using either
an internal or external capacitor. Included on the chip
are precision 100pF integration capacitors, hold and
reset switches, and output multiplexers.
As a complete circuit on a single chip, the ACF2101
eliminates many of the problems commonly encoun-
tered in discrete designs, such as leakage current errors
and noise pickup. The integrating approach can pro-
vide lower noise than conventional transimpedance
amplifier designs and also eliminates the need for high
performance, high value feedback resistors.
The extremely low bias current and low noise of the
ACF2101’s Difet ® amplifiers, along with active la-
ser trimming of both offset and drift, assure precision
current to voltage conversion.
Although designed for +5V, –15V supplies, the
ACF2101 can be operated on supplies up to ±18VDC.
It is available in both 24-pin plastic DIP and SOIC
packages.
Difet® Burr-Brown Corp.
Cap A
In A
Sw In A
Com A
Cap B
In B
Sw In B
Com B
Reset
AB
Hold
AB
CINTERNAL
100pF
Reset
Hold
Select
AB
A
Select
Hold
CINTERNAL
100pF
Reset
B
Select
AB
V+ Gnd V–
Out A
Sw Out A
Sw Com A
Out B
Sw Out B
Sw Com B
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1990 Burr-Brown Corporation
PDS-1078D
Printed in U.S.A. September, 1994
1 page  
DICE INFORMATION
ACF2101 DIE TOPOGRAPHY
PAD
1
2
3
4
5
6
7
8
9
10
11
12
FUNCTION
A Out
A Ground
A Common
A Cap
A In
A Switch-In
B Switch-In
B In
B Cap
B Common
B Ground
B Out
Substrate Bias: Ground.
PAD
13
14
15
16
17
18
19
20
21
22
23
24
FUNCTION
B Switch-Out
B Switch-Common
B Select
B Reset
B Hold
V–
V+
A Hold
A Reset
A Select
A Switch-Common
A Switch-Out
MECHANICAL INFORMATION
Die Size
Die Thickness
Min. Pad Size
Backing
MILS (0.001")
132 x 157 ±5
20 ±3
4x4
MILLIMETERS
3.35 x 3.99 ±0.13
0.51 ±0.08
0.10 x 0.10
None
®
5 ACF2101
5 Page 
Charge Transfer
Charge transfer is the charge that is coupled from the logic
control inputs through circuit capacitance to the integration
capacitor when the Hold and Reset switches change mode.
Careful printed circuit layout must be used to minimize
external coupling from digital to analog circuitry and the
resulting charge transfer. Charge transfer results in a DC
charge offset error voltage. The ACF2101 switches are
compensated to reduce charge transfer errors.
Since the ACF2101 switches contribute equal and opposite
charge for positive and negative logic input transitions, the
total error due to charge transfer is determined by the
switching sequence. For each switch, a logic transition
results in a specific charge (and offset voltage) while an
opposite going logic transition results in an opposite charge
(and opposite offset voltage). Thus, if the Hold switch is
turned on and off during one integration cycle, the total
charge transfer at the end of the sequence due to the Hold
switch is essentially zero.
The amount of charge transfer to the integration capacitor is
constant for each switch. Therefore, the charge offset error
voltage is lower for larger integration capacitors. The
ACF2101’s 0.1pC charge transfer results in a 1mV charge
offset voltage when using the 100pF internal integration
capacitor. The offset voltage will change linearly with the
integration capacitance. That is, 50pF will result in a 2mV
charge offset and 200pF in a 0.5mV charge offset.
Droop
Droop is the change in the output voltage over time as a
result of the bias current of the amplifier, leakage of the
integration capacitor and leakage of the Reset and Hold
switches. Droop occurs in both the Integrate and Hold
modes of operation. Careful printed circuit layout must be
used to minimize external leakage currents as discussed
previously.
The droop is calculated by the equation:
Droop =
100fA
CINTEGRATION
where CINTEGRATION = CINTERNAL + CEXTERNAL and is the
integration capacitance in farads and the result is in volts per
second. For the internal integration capacitance of 100pF,
the droop is calculated as:
Droop
=
100
100
X
X
10 –15
10 –12
= 1mV/s or 1nV/µs
Droop increases by a factor of 2 for each 10°C increase
above 25°C. See the typical performance curve showing
Bias Current vs Temperature.
Capacitive Loads
Any capacitive load can be safely driven through the multi-
plexed output of the ACF2101. As with any op amp, how-
ever, best dynamic performance of the ACF2101 can be
achieved by minimizing the capacitive load. See the typical
performance curve showing settling time as a function of
capacitive load for more information. A large capacitive
0
INTEGRATE
HOLD RESET HOLD
–10
OFF
HOLD
ON
OFF
RESET
ON
Charge Offset
MODES OF O1PmERVAT*ION
Droop
1nV/µs*
Ideal Level
* 100pF Integration
Capacitor
FIGURE 8. Droop and Charge Offset Effects.
load is often useful in reducing the noise of systems not
requiring the full bandwidth of the ACF2101.
PROGRAMMABLE I TO V CONVERTER EXAMPLE
Figure 10 illustrates the use of the ACF2101 as a program-
mable current to voltage converter. The output of the circuit,
VOUT, is a DC level for a constant current input. The timing
diagram shown in Figure 9 shows VOUT for an input current
that varies from one sample to the next. This circuit offers
wide dynamic range without the use of extremely large
resistors. An ACF2101 and an OPA2107 op amp are config-
ured to convert a low level input current to an output voltage.
The equivalent gain of the converter is determined by the
frequency of the digital input signal, fS. The inherent inte-
grating function of the ACF2101 is very useful for rejection
of noise such as power line pickup.
The ACF2101 integrates the current signal for the period of
fS. The magnitude of the ramp voltage at the output of the
ACF2101 is a function of the frequency of fS and the value
of the integration capacitor, CINTEGRATION. The ACF2101’s
100pF internal capacitor is used for CINTEGRATION in this
example. The effect is that fS controls the equivalent feed-
back resistance of a transconductance (current-to-voltage)
amplifier. The equivalent feedback resistance range can vary
over a large range of at least 1MΩ to 1GΩ as illustrated in
the accompanying table. Larger equivalent feedback resis-
tances can be obtained if internal capacitances smaller than
100pF are used with the ACF2101.
A simplified equation for the operation of this circuit is:
VOUT = ISENSOR X RPROGRAM
Where:
VOUT is the voltage at the output of the OPA2107,
ISENSOR is the current into the ACF2101, and
RPROGRAM is the equivalent feedback resistance of the
circuit calculated by the equation,
RPROGRAM = 1/(fS X CINTEGRATION) = 1/(fS X 100pF)
®
11 ACF2101
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ACF2101.PDF ] | |
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