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PDF ACD2202S8P0 Data sheet ( Hoja de datos )
| Número de pieza | ACD2202S8P0 | |
| Descripción | CATV/TV/Video Downconverter with Dual Synthesizer | |
| Fabricantes | ANADIGICS Inc | |
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FEATURES
• Integrated Downconverter
• Integrated Dual Synthesizer
• 256 QAM Compatibility
• Single +5 V Power Supply Operation
• Low Power Consumption: <0.6 W
• Low Noise Figure: 8 dB
• High Conversion Gain: 10 dB
• Low Distortion: -53 dBc
• Three-Wire Interface
• Small Size
• -40 °C to +85 °C
ACD2202
CATV/TV/Video Downconverter
with Dual Synthesizer
Data Sheet - Rev 2.1
APPLICATIONS
• Set Top Boxes
• CATV Video Tuners
• Digital TV Tuners
• CATV Data Tuners
• Cable Modems
PRODUCT DESCRIPTION
The ACD2202 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions in a double conversion tuner gain block,
local oscillator, balanced mixer and dual synthesizer.
The specifications meet the requirements of
CATV/TV/Video and Cable Modem Data applications.
The ACD2202 is supplied in a 28 lead SSOP
package and requires a single +5 V supply voltage.
S8 Package
28 Pin SSOP
The IC is well suited for applications where small
size, low cost, low auxiliary parts count and a no-
compromise performance is important. It provides
for cost reduction by lowering the component and
packaged IC count and decreasing the amount of
labor-intensive production alignment steps, while
significantly improving performance and reliability.
RFD
RF2: 64/65
Prescaler
18 Bit RF2
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
CPD
RFIN+
RFIN-
Low Noise
VGA
Mixer
VIF+IFOUT+
VIF+IFOUT-
REFIN
REFOUT
Oscillator
15 Bit RF2
R Counter
15 Bit RF1
R Counter
Phase Splitter
RFU
RF1: 64/65
Prescaler
18 Bit RF1
N Counter
RF1
Phase
Detector
RF1
Charge
Pump
CPU
TCKT
OSC OUT
Figure 1: Downconverter Block Diagram
Clock
Data
Enable
22 Bit
Data Registar
Figure 2: Dual Synthesizer Block Diagram
12/2003
1 page  
Table 4: Electrical Specifications - Downconverter Section
(TA = 25 °C(7), VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
PARAMETER
MIN TYP MAX
UNIT
Conversion Gain (1)
Conversion Gain (2)
8 10 14
11 13 17
dB
SSB Noise Figure (2), (3)
- 4 7 dB
Cross Modulation (2), (4), (6)
-
-56 -53
dBc
3rd Order Intermodulation Distortion
(IMD3) (2), (5), (6)
- - -53 dBc
2-Tone 3rd Order Input Intercept Point
(IIP3) (2), (5), (6)
+12 -
- dBm
LO Phase Noise (@ 10 KHz Offset) (1), (2)
-
-90 -85.5 dBc/Hz
LO Output Power (pin 24) (1), (2)
-10 -5 - dBm
Spurious @ IF Output
LO Signals and Harmonics
Beats Within Output Channel
Other Beats from 2 to 200 MHz
Other Spurious
- -10 - dBm
- -48 -
dBc
- -50 - dBm
- -10 - dBm
IF Supply Current (pin 27 & 28) (1), (2),(6)
- 50 65 mA
Osc/Phase Splitter Supply Current
(pin 25)
- 30 45 mA
Power Consumption
-
400 550
mW
Notes:
(1) As measured in ANADIGICS test fixture with single-ended RF input.
(2) As measured in ANADIGICS test fixture with differential RF inputs.
(3) SSB noise figure will be approximately 3 dB higher with single-ended RF input.
(4) Two tones: 1085 and 1091 MHz, -20 dBm each, 1091 MHz tone AM-modulated
99% at 15 kHz.
(5) Two tones: 1085 and 1091 MHz, -15 dBm each.
(6) R1 = 10 Ohms.
(7) Case Temperature is 15 °C higher than Ambient Temperature, when Ambient
Temperature is +25 °C, using the PC Board Layout shown in Figures 23-25.
ACD2202
Data Sheet - Rev 2.1
12/2003
5
5 Page 
LOGIC PROGRAMMING
Synthesizer Register Programming
The ACD2202 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
ACD2202
Table 7: Register Select Bits
SELECT
BITS
SS
21
DESTINATION REGISTER FOR
SERIAL DATA
0 0 Reference Divider Register for PLL2
0 1 Main Divider Register for PLL2
1 0 Reference Divider Register for PLL1
1 1 Main Divider Register for PLL1
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
MSB
Table 8: Reference Divider Registers
LSB
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Program Mode
Reference Divider Divide Ratio, R
Select
D D D D D R R R R R R R RRRRRRRR S S
5 4 3 2 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 2 1
Table 9: Reference Divider R Counter Bits
DIVIDE R R R R R R R R R R R R R R R
RATIO R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
3 0000000000000 11
4 0000000 0 0000 100
- ---------------
32767
1 1 1 1 1 1 1 1 1 1 1 1 1 11
Notes:
Divide ratios less than 3 are prohibited.
Data Sheet - Rev 2.1
12/2003
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet ACD2202S8P0.PDF ] | |
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