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AAT3532IAS-B1 Schematic ( PDF Datasheet ) - Advanced Analogic Technologies

Teilenummer AAT3532IAS-B1
Beschreibung MicroPower Microprocessor Reset Circuit
Hersteller Advanced Analogic Technologies
Logo Advanced Analogic Technologies Logo 




Gesamt 8 Seiten
AAT3532IAS-B1 Datasheet, Funktion
AAT3532
MicroPower™ Microprocessor Reset Circuit
General Description
The AAT3532 PowerManager™ product is a mem-
ber of AATI’s Total Power Management ICs™
(TPMIC™) product family. It is a fully integrated
device for monitoring microprocessor activity,
external reset, and power supply conditions. The
device holds the microprocessor in a reset condi-
tion for a minimum of 250ms while VCC is estab-
lished to ensure correct system start-up. A manual
reset can be initiated via a de-bounced input pin.
As an additional level of protection, the AAT3532
includes a watchdog timer which requires a period-
ic strobe input from the microprocessor to ensure
correct operation. The AAT3532 has a programma-
ble watchdog timer and voltage tolerance level.
The quiescent supply current is extremely low, typ-
ically 23µA.
The AAT3532 is available in an 8-pin SOP package
specified over -40° to 85°C temperature range.
Features
PowerManager
• Adjustable 4.5V or 4.75V Voltage Monitor
• 250ms (min) Reset Pulse Width
• Low quiescent current: typically 23µA
• Adjustable Watchdog Timer (150ms, 600ms,
or 1200ms)
• De-bounced Manual Reset Input
• Operates down to 20ns strobe input pulse
width
• No external components
• Temp range -40° to 85°C
• Standard 8 pin SOP package
• Pin compatible with MAX1232
Applications
• Computers
• Controllers
• Telecom Equipment
• Embedded Systems
• Intelligent Instrumentation
• Automotive
Typical Application
VDD
VCC
PBRST
AAT3532
TD
TOL
GND
RST
RST
ST
VDD
RESET
INPUT
µP
I/O
3532.2001.11.0.9
1






AAT3532IAS-B1 Datasheet, Funktion
AAT3532
MicroPower™ Microprocessor Reset Circuit
Applications Information
Manual Reset
The PBRST pin makes it possible to manually
reset the system by either directly connecting a
mechanical push-button between the PBRST pin
PBRST
tPBD
tPB
and GND or connecting to a logic low output.
Internal de-bounce circuitry is provided to reduce
the effect of noise glitches at the input. The signal
should remain low for a minimum of 20ms for cor-
rect operation. Once the PBRST signal is released
(or goes to a logic high), RESET (RESET) remains
asserted for a minimum of 250ms.
RESET
RESET
Figure 2 Push-button Reset
Watchdog Timer
The watchdog timer monitors the microprocessor
to ensure that the system is functioning correctly.
The ST pin of the AAT3532 can be derived from the
microprocessor data signals, address signals,
and/or I/O signals. The watchdog timer function
forces the RST and RST signals into the active
state when the ST input is not toggled by a pre-
determined time. This time period is set by the logic
state of the TD pin as shown in Table 1. The timer
tRST
starts once the RST signals become inactive. If the
watchdog timer does not receive a high-to-low tran-
sition within the specified timeout period, then the
RST signals are activated for a minimum 250ms. In
normal operation the timer should receive a transi-
tion from the microprocessor within the timeout
period, in which case the timer is reset and normal
operation continues.
The AAT3532 will accept and recognize ST pulses
down to a minimum of 20ns wide.
Figure 3. Watchdog Input
tST
ST
tTD
6 3532.2001.11.0.9

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