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AAT3215IGV-29-T1 Schematic ( PDF Datasheet ) - Advanced Analogic Technologies

Teilenummer AAT3215IGV-29-T1
Beschreibung 150mA CMOS High Performance LDO
Hersteller Advanced Analogic Technologies
Logo Advanced Analogic Technologies Logo 




Gesamt 16 Seiten
AAT3215IGV-29-T1 Datasheet, Funktion
AAT3215
150mA CMOS High Performance LDO
General Description
The AAT3215 MicroPower™ Low Dropout Linear
Regulator is ideally suited for portable applications
where low noise, extended battery life and small
size are critical. The AAT3215 has been specifi-
cally designed for very low output noise perform-
ance, fast transient response and high power sup-
ply rejection ratio (PSRR), making it ideal for pow-
ering sensitive RF circuits.
Other features include low quiescent current, typi-
cally 95µA, and low dropout voltage which is typi-
cally less than 140mV at full output current. The
device is output short circuit protected and has a
thermal shutdown circuit for additional protection
under extreme conditions.
The AAT3215 also features a low-power shutdown
mode for extended battery life. A reference bypass
pin has been provided to improve PSRR perform-
ance and output noise, by connecting an external
capacitor from the AAT3215's reference output to
ground.
The AAT3215 is available in a space saving 5-pin
SOT-23 or 8-pin SC70-JW package in 8 factory
programmed voltages of 2.5V, 2.7V, 2.8V, 2.85V,
2.9V, 3.0V, 3.3V, or 3.5V.
Features
PowerLinear
• Low Dropout - 140mV at 150mA
• Guaranteed 150mA Output
• High accuracy ±1.5%
• 95µA Quiescent Current
• High Power Supply Ripple Rejection
• 70 dB at 1kHz
• 50 dB at 10kHz
• Very low self noise 45µVrms/rtHz
• Fast line and load transient response
• Short circuit protection
• Over-Temperature protection
• Uses Low ESR ceramic capacitors
• Noise reduction bypass capacitor
• Shutdown mode for longer battery life
• Low temperature coefficient
• 8 Factory programmed output voltages
• SOT-23 5-pin or SC70-JW 8-pin package
Applications
• Cellular Phones
• Notebook Computers
• Portable Communication Devices
• Personal Portable Electronics
• Digital Cameras
Typical Application
VIN
IN OUT
AAT3215
VOUT
ON/OFF EN
BYP
GND
1µF
10nF
2.2µF
GND
GND
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AAT3215IGV-29-T1 Datasheet, Funktion
AAT3215
150mA CMOS High Performance LDO
Typical Characteristics
(Unless otherwise noted, VIN = 5V, TA = 25°C)
Output Self Noise
500
0
10 100
1k 10k 100k
Frequency (Hz)
1m
10m
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AAT3215IGV-29-T1 pdf, datenblatt
AAT3215
150mA CMOS High Performance LDO
Applications Information
High Peak Output Current Applications
Some applications require the LDO regulator to
operate at continuous nominal level with short
duration high current peaks. The duty cycles for
both output current levels must be taken into
account. To do so, one would first need to calcu-
late the power dissipation at the nominal continu-
ous level, then factor in the additional power dissi-
pation due to the short duration high current peaks.
For example, a 2.5V system using a AAT3215IGV-
2.5-T1 operates at a continuous 100mA load cur-
rent level and has short 150mA current peaks. The
current peak occurs for 378µs out of a 4.61ms peri-
od. It will be assumed the input voltage is 4.2V.
First the current duty cycle in percent must be cal-
culated:
% Peak Duty Cycle: X/100 = 378µs/4.61ms
% Peak Duty Cycle = 8.2%
The LDO Regulator will be under the 100mA load
for 91.8% of the 4.61ms period and have 150mA
peaks occurring for 8.2% of the time. Next, the
continuous nominal power dissipation for the
100mA load should be determined then multiplied
by the duty cycle to conclude the actual power dis-
sipation over time.
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)
PD(100mA) = (4.2V - 2.5V)100mA + (4.2V x 150µA)
PD(100mA) = 170.6mW
PD(91.8%D/C) = %DC x PD(100mA)
PD(91.8%D/C) = 0.918 x 170.6mW
PD(91.8%D/C) = 156.6mW
The power dissipation for 100mA load occurring for
91.8% of the duty cycle will be 156.6mW. Now the
power dissipation for the remaining 8.2% of the
duty cycle at the 150mA load can be calculated:
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND)
PD(150mA) = (4.2V - 2.5V)150mA + (4.2V x 150mA)
PD(150mA) = 255.6mW
PD(8.2%D/C) = %DC x PD(150mA)
PD(8.2%D/C) = 0.082 x 255.6mW
PD(8.2%D/C) = 21mW
The power dissipation for 150mA load occurring for
8.2% of the duty cycle will be 21mW. Finally, the
12
two power dissipation levels can summed to deter-
mine the total true power dissipation under the var-
ied load.
PD(total) = PD(100mA) + PD(150mA)
PD(total) = 156.6mW + 21mW
PD(total) = 177.6mW
The maximum power dissipation for the AAT3215
operating at an ambient temperature of 85°C is
211mW. The device in this example will have a total
power dissipation of 177.6mW. This is well within
the thermal limits for safe operation of the device.
Printed Circuit Board Layout
Recommendations
In order to obtain the maximum performance from
the AAT3215 LDO regulator, very careful attention
must be considered in regard to the printed circuit
board (PCB) layout. If grounding connections are
not properly made, power supply ripple rejection,
low output self noise and transient response can
be compromised.
Figure 1 shows a common LDO regulator layout
scheme. The LDO Regulator, external capacitors
(CIN, COUT and CBYP) and the load circuit are all con-
nected to a common ground plane. This type of lay-
out will work in simple applications where good
power supply ripple rejection and low self noise are
not a design concern. For high performance appli-
cations, this method is not recommended.
The problem with the layout in Figure 1 is the bypass
capacitor and output capacitor share the same
ground path to the LDO regulator ground pin along
with the high current return path from the load back
to the power supply. The bypass capacitor node is
connected directly to the LDO regulator internal ref-
erence, making this node very sensitive to noise or
ripple. The internal reference output is fed into the
error amplifier, thus any noise or ripple from the
bypass capacitor will be subsequently amplified by
the gain of the error amplifier. This effect can
increase noise seen on the LDO regulator output as
well as reduce the maximum possible power supply
ripple rejection. There is PCB trace impedance
between the bypass capacitor connection to ground
and the LDO regulator ground connection. When
the high load current returns through this path, a
small ripple voltage is created, feeding into the CBYP
loop.
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