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A8351601-40 Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A8351601-40
Beschreibung Bar Code Reader
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 30 Seiten
A8351601-40 Datasheet, Funktion
A8351601 Series
Bar Code Reader
Document Title
Bar Code Reader
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
1.0
History
Initial issue
Change document title from “Bar Code Reader” to
“8 Bit Microcontroller”
Error correction:
(1) Delete single-step operation description
(2) Delete “the only exit from power down is a hardware
reset” on page 32
Modify 44L QFP package outline drawing and dimensions
Modify PWM function
(1) Add PWM3 delay control bits D0, D1 and D2
(2) Add PWM4 output control bit PWM1.7
Error correction:
Delete Functional Description
Change document title from “8 Bit Microcontroller” to
“Bar Code Reader”
Modify AC, DC Electrical Characteristics:
Add 3V ± 10% condition
SFR Map address has some typewriting errors
Modify DC and AC Electrical Characteristics
Final version release
Issue Date
June 5, 2000
June 22, 2000
Remark
Preliminary
November 15, 2000
January 17, 2001
June 6, 2001
October 16, 2001
February 19, 2002
July 12, 2002
Final
(July, 2002, Version 1.0)
AMIC Technology, Inc.






A8351601-40 Datasheet, Funktion
A8351601 Series
Pin Description (continued)
Symbol
P3.0-P3.7
PSEN
RST
PWM1
PWM2
PWM3
PWM4
XTAL1
XTAL2
GND
VCC
P-DIP
10-17
10
11
12
13
14
15
16
17
29
9
19
18
20
40
Pin No.
PLCC
11,13-19
11
13
14
15
16
17
18
19
32
10
1
12
23
34
21
20
22
44
QFP
5, 7-13
5
7
8
9
10
11
12
13
26
4
39
6
17
28
15
14
16
38
I/O Description
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled
high by the internal pullups and can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will source
current because of the internal pullups. (See DC
Characteristics: IIL).
Port 3 also serves the special features of the A8351601, as
listed below:
I RxD (P3.0): Serial input port.
O TxD (P3.1): Serial output port.
I INT0 (P3.2): External interrupt 0.
I INT1 (P3.3): External interrupt 1.
I T0 (P3.4): Timer 0 external input.
I T1 (P3.5): Timer 1 external input.
O WR (P3.6): External data memory write strobe.
O RD (P3.7): External data memory read strobe.
O Program Store Enable: The read strobe to external
program memory. When the device is executing code from
the external program memory, PSEN is activated twice
each machine cycle except that two PSEN actives are
skipped during each access to external data memory.
PSEN is not activated during fetches from internal program
memory.
I Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device.
O Pulse width modulation 1 output.
O Pulse width modulation 2 output.
O (D2, D1, D0) controlled the delay time of PWM3 from 4 CLK
to 11 CLK after PWM1 change.
O PWM1.7: 1 is PWM3/4096, 75% duty (3072 PWM3 cycle
high, 1024 PWM3 cycle low)
PWM1.7: 0 is PWM3/1024, 67% duty (2048 PWM3 cycle
high, 1024 PWM3 cycle low)
I Crystal 1: Input to the inverting oscillator and input to the
internal clock generator circuits.
O Crystal 2: Output from the inverting oscillator.
I Ground: 0V reference.
I Power Supply: This is the power supply voltage for
operation.
(July, 2002, Version 1.0)
5 AMIC Technology, Inc.

6 Page









A8351601-40 pdf, datenblatt
A8351601 Series
T2CON: (continued)
76
TF2 EXF2
Register Description:
EXEN2
T2CON.3
TR2
C/ T2
CP/ RL2
T2CON.2
T2CON.1
T2CON.0
Notes:
Timer 2 Operating Modes
RCLK + TCLK
0
0
1
CP/ RL2
0
1
X
5
RCLK
4
TCLK
3
EXEN2
2
TR2
1
C/ T2
0
CP/ RL2
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
negative transition on T2EX if Timer 2 is not being used to clock the Serial Port, EXEN2 = 0
causes Timer 2 to ignore events at T2EX.
Software START/STOP control for Timer 2. A logic 1 starts the Timer.
Timer or Counter select. 0 = Internal Timer. 1 = External Event Counter (triggered by falling
edge).
Capture/Reload flag. When set, captures occur on negative transitions at T2EX if EXEN2
=1. When cleared, auto-reloads occur either with Timer 2 overflows or negative transitions
at T2EX when EXEN2=1. When either RCLK=1 or TCLK=1, this bit is ignored and the Timer
is forced to auto-reload on Timer 2 overflow.
TR2 MODE
1 16-Bit Auto-Reload
1 16-Bit Capture
1 Baud Rate Generator
ADD(A1H):
Extra Additional Register. Not Bit Addressable.
76543210
-
-
Delay2
Delay1
Delay0
T2EXREV
DF
RAMDIS
Register Description:
- Not implemented, reserve for future use.
- Not implemented, reserve for future use.
D2 PWM3 delay control bit.
D1 PWM3 delay control bit.
D0 PWM3 delay control bit.
T2EXREV T2EX reverse control bit. Set/Cleared by software specify T2EX pin reverse/no reverse.
DF Double system frequency control bit. Set/Cleared by software specify Xtal frequency *2 / Xtal frequency.
RAMDIS
Build in 8K bytes SRAM enable/disable control bit. Set/Cleared by software specify
Enable/disable build in 8K bytes SRAM.
Bit <5:3>
Delay
0
4 CLK
1
5 CLK
2
6 CLK
3
7 CLK
(D2, D1, D0) controlled the delay time of PWM3 after PWM1 change.
4
8 CLK
5
9 CLK
6
10 CLK
7
11 CLK
(July, 2002, Version 1.0)
11 AMIC Technology, Inc.

12 Page





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