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Teilenummer | A67L83181E-11 |
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Beschreibung | 256K X 16/18/ 128K X 32/36 LVTTL/ Flow-through DBA SRAM | |
Hersteller | AMIC Technology | |
Logo | ||
Gesamt 19 Seiten A67L83161/A67L83181/
A67L73321/A67L73361 Series
Preliminary
256K X 16/18, 128K X 32/36
LVTTL, Flow-through DBATM SRAM
Document Title
256K X 16/18, 128K X 32/36 LVTTL, Flow-through DBATM SRAM
Revision History
Rev.
N0.o0.
0.1
History
Initial issue
Change fast access time from 7.5/8.0/8.5/9.0 ns to 10/11/12
nCshange set-up time from 2.0/2.2/2.5 ns to 2.5 ns
Fix pin assignment error for pin 14 and pin 16
Issue Date
April 7, 1999
September 15, 1999
Remark
Preliminary
PRELIMINARY (September, 1999, Version 0.1)
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc
AMIC Technology, Inc.
A67L83161/A67L83181/
A67L73321/A67L73361 Series
Pin Description
Pin No.
LQFP (X16/X18) LQFP (X32/X36)
37
36
35,34,33,32,
100,99,82,81,
44,45,46,47,
48,49,50
80
37
36
35,34,33,32,
100,99,82,81,
44,45,46,47,
48,49,50
93 (BW1)
94 (BW2 )
93 (BW1)
94 (BW2 )
95 (BW3 )
96 (BW4 )
89 89
98 98
92 92
97 97
86 86
85 85
Symbol
A0
A1
A2 - A16
A17
BW1
BW2
BW3
BW4
CLK
CE
CE2
CE2
OE
ADV/ LD
Description
Synchronous Address Inputs : These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. Pins 83 and 84 are reserved as address bits
for higher-density 9Mb and 18Mb DBA SRAMs, respectively.
A0 and A1 are the two lest significant bits (LSB) of the
address field and set the internal burst counter if burst is
desired.
Synchronous Byte Write Enables : These active low inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address, BWs are associated with
addresses and apply to subsequent data. BW1 controls I/Oa
pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins;
BW4 controls I/Od pins.
Clock : This signal registers the address, data, chip
enables, byte write enables and burst control inputs on its
rising edge. All synchronous inputs must meet setup and
hold times around the clock’s rising edge.
Synchronous Chip Enable : This active low input is used to
enable the device. This input is sampled only when a new
external address is loaded (ADV/LD LOW).
Synchronous Chip Enable : This active low input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD LOW). This input can be used
for memory depth expansion.
Output Enable : This active low asynchronous input enables
the data I/O output drivers.
Synchronous Address Advance/Load : When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is loaded.
When HIGH, R/ W is ignored. A LOW on this pin permits a
new address to be loaded at CLK rising edge.
PRELIMINARY (September, 1999, Version 0.1)
5
AMIC Technology, Inc.
6 Page ICC Operating Condition and Maximum Limits
Symbol
Parameter
Max.
-10 -11
Power Supply Current :
ICC Operating
400 300
ICC1 Power Supply Current : Idle
18
12
ISB2 CMOS Standby
ISB3 TTL Standby
ISB4 Clock Running
ISB2Z SLEEP Mode
10 10
25 25
85 65
10 10
A67L83161/A67L83181/
A67L73321/A67L73361 Series
Unit
-12
Conditions
Device selected; All inputs ≤ VIL
250 mA or ≥ VIH; Cycle time ≥ tKC (MIN);
VCC = MAX; Output open
Device selected; VCC = MAX;
10
mA
CEN ≥ VIH;
All inputs ≤ VSS+0.2 or ≥VCC-0.2;
Cycle time ≥ tKC (MIN)
Device deselected; VCC = MAX;
10 mA All inputs ≤VSS+0.2 or ≥ VCC-0.2;
All inputs static; CLK frequency=0
Device deselected; VCC = MAX;
25 mA
All inputs ≤ VIL; or ≥ VIH;
All inputs static; CLK frequency=0
Device deselected; VCC = MAX;
60 mA All inputs ≤ VSS+0.2 or ≥ VCC-0.2;
Cycle time ≥ tKC (MIN)
10 mA
ZZ ≥ VIH
PRELIMINARY (September, 1999, Version 0.1)
11
AMIC Technology, Inc.
12 Page | ||
Seiten | Gesamt 19 Seiten | |
PDF Download | [ A67L83181E-11 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
A67L83181E-10 | 256K X 16/18/ 128K X 32/36 LVTTL/ Flow-through DBA SRAM | AMIC Technology |
A67L83181E-11 | 256K X 16/18/ 128K X 32/36 LVTTL/ Flow-through DBA SRAM | AMIC Technology |
A67L83181E-12 | 256K X 16/18/ 128K X 32/36 LVTTL/ Flow-through DBA SRAM | AMIC Technology |
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