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PDF A63L7332E-42 Data sheet ( Hoja de datos )
| Número de pieza | A63L7332E-42 | |
| Descripción | 128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined Data Output | |
| Fabricantes | AMIC Technology | |
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A63L7332 Series
Preliminary
128K X 32 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Document Title
128K X 32 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined
Data Output
Revision History
Rev. No.
0.0
1.0
1.1
1.2
History
Initial issue
Change fast access times from 4.5/5 ns to 4.2/4.5/5.0 ns
Change DC and operating characteristics -
ICC1 (Max.) : 300mA to 350mA
ISB1 (Max.) : 25mA to 38mA
Modify 100-pin LQFP symbol y dimensions -
Max. in mm :0.08 → 0.1
Max. in inches : 0.003 → 0.004
Issue Date
June 02, 1998
August 27, 1998
December 18, 1998
Remark
Preliminary
December 31, 1998
PRELIMINARY (December, 1998, Version 1.2)
AMIC Technology, Inc.
1 page  
A63L7332 Series
Pin Description
Pin No.
32 - 37, 44 - 50, 81, 82,
99, 100
89
87, 93 - 96
88
86
92, 97, 98
83
84
85
31
Symbol
A0 - A16
CLK
BWE , BW1 - BW4
GW
OE
CE2 ,CE2, CE
ADV
ADSP
ADSC
MODE
64 ZZ
2, 3, 6 - 9, 12, 13, 18, 19,
22 - 25, 28, 29, 52, 53,
56 - 59, 62, 63, 68, 69,
72 - 75, 78, 79
1, 14, 16, 30, 38, 39, 42,
43, 51, 66, 80
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
I/O1- I/O32
NC
VCC
GND
VCCQ
GNDQ
Address Inputs
Description
Clock
Byte Write Enables
Global Write
Output Enable
Chip Enables
Burst Address Advance
Processor Address Status
Controller Address Status
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
Data Inputs/Outputs
No Connection
Power Supply
Ground
Isolated Output Buffer Supply
Isolated Output Buffer Ground
PRELIMINARY (December, 1998, Version 1.2)
4
AMIC Technology, Inc.
5 Page 
A63L7332 Series
AC Characteristics (continued)
Symbol
Parameter
Hold Times
tAH Address
tADVH
Address Status
( ADSC , ADSP )
tAAH Address Advance ( ADV )
tWH Write Signal
( BW1 , BW2 , BW3 ,
BW4 , BWE , GW )
tDH Data-in
tCEH Chip Enable
( CE , CE2, CE2 )
-4.2
Min. Max.
-4.5
Min. Max.
-5.0
Min. Max.
Unit
Note
0.5 - 0.5 - 0.5 -
0.5 - 0.5 - 0.5 -
0.5 - 0.5 - 0.5 -
0.5 - 0.5 - 0.5 -
ns 7, 9
ns 7, 9
ns 7, 9
ns 7, 9
0.5 - 0.5 - 0.5 -
0.5 - 0.5 - 0.5 -
ns 7, 9
ns 7, 9
Notes:
1. All voltages refer to GND.
2. Overshoot: VIH ≤+4.6V for t ≤tKC/2.
Undershoot: VIH ≥ -0.7V for t ≤tKC/2.
Power-up: VIH ≤+3.6 and VCC ≤3.1V
for t ≤200ms
3. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
4. Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
5. For output loading, CL = 5pF, as shown in Figure 2. Transition is measured ±150mV from steady state voltage.
6. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tQELZ.
7. A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
8. OE has no effect when a Byte Write enable is sampled LOW.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
10. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
11. "Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
12. MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10µA.
13. Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
PRELIMINARY (December, 1998, Version 1.2)
10
AMIC Technology, Inc.
11 Page | ||
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| PDF Descargar | [ Datasheet A63L7332E-42.PDF ] | |
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