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A62S8308M-70SI Schematic ( PDF Datasheet ) - AMIC Technology

Teilenummer A62S8308M-70SI
Beschreibung 256K X 8 BIT LOW VOLTAGE CMOS SRAM
Hersteller AMIC Technology
Logo AMIC Technology Logo 




Gesamt 17 Seiten
A62S8308M-70SI Datasheet, Funktion
A62S8308 Series
Preliminary
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Document Title
256K X 8 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue
Modify VCCmax from 3.3V to 3.6V
Add 55ns grade spec. for VCC = 3.0V to 3.6V
Issue Date
December 6, 1999
December 20, 2000
March 23, 2001
Remark
Preliminary
PRELIMINARY (March, 2001, Version 0.2)
AMIC Technology, Inc.






A62S8308M-70SI Datasheet, Funktion
A62S8308 Series
AC Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.6V)
Symbol
Parameter
A62S8308-55S/SI
A62S8308-70S/SI
Unit
(VCC = 3.0V to 3.6V) (VCC = 2.7V to 3.6V)
Min.
Max.
Min.
Max.
Read Cycle
tRC Read Cycle Time
55 - 70 - ns
tAA Address Access Time
- 55 - 70 ns
tACE1
Chip Enable Access Time
CE1 - 55 - 70 ns
tACE2
CE2 - 55 - 70 ns
tOE Output Enable to Output Valid
- 30 - 35 ns
tCLZ1
Chip Enable to Output in Low Z
CE1 10
-
10
- ns
tCLZ2
CE2 10 - 10 - ns
tOLZ Output Enable to Output in Low Z
5 - 5 - ns
tCHZ1
Chip Disable to Output in High Z
CE1
0
20
0
25 ns
tCHZ2
CE2 0 20 0 25 ns
tOHZ Output Disable to Output in High Z
0 20 0 25 ns
tOH Output Hold from Address Change
5 - 10 - ns
Read Cycle
tWC Write Cycle Time
55 - 70 - ns
tCW Chip Enable to End of Write
50 - 60 - ns
tAS Address Setup Time
0 - 0 - ns
tAW Address Valid to End of Write
50 - 60 - ns
tWP Write Pulse Width
40 - 50 - ns
tWR Write Recovery Time
0 - 0 - ns
tWHZ Write to Output in High Z
0 25 0 25 ns
tDW Data to Write Time Overlap
25 - 30 - ns
tDH Data Hold from Write Time
0 - 0 - ns
tOW Output Active from End of Write
5 - 5 - ns
Notes: tCHZ1, tCHZ2, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
PRELIMINARY (March, 2001, Version 0.2)
5
AMIC Technology, Inc.

6 Page









A62S8308M-70SI pdf, datenblatt
Low VCC Data Retention Waveform (1) ( CE1 Controlled)
VCC
CE1
2.7V
tCDR
VIH
DATA RETENTION MODE
VDR 2V
CE1 VDR - 0.2V
Low VCC Data Retention Waveform (2) (CE2 Controlled)
VCC
CE2
2.7V
tCDR
VIL
DATA RETENTION MODE
VDR 2V
CE2 < 0.2V
A62S8308 Series
2.7V
tR
VIH
2.7V
tR
VIL
PRELIMINARY (March, 2001, Version 0.2)
11
AMIC Technology, Inc.

12 Page





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A62S8308M-70SI256K X 8 BIT LOW VOLTAGE CMOS SRAMAMIC Technology
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