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PDF A62S7316G-55S Data sheet ( Hoja de datos )
| Número de pieza | A62S7316G-55S | |
| Descripción | 128K X 16 BIT LOW VOLTAGE CMOS SRAM | |
| Fabricantes | AMIC Technology | |
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A62S7316 Series
Preliminary
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
128K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
Rev. No.
0.0
0.1
0.2
History
Initial issue
Modify VCCmax from 3.3V to 3.6V
Add 55ns grade spec. for VCC = 3.0V to 3.6V
Issue Date
November 24, 1999
December 20, 2000
March 23, 2001
Remark
Preliminary
PRELIMINARY (March, 2001, Version 0.2)
AMIC Technology, Inc.
1 page  
A62S7316 Series
Absolute Maximum Ratings*
VCC to GND . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V
IN, IN/OUT Volt to GND . . . . . . . . -0.5V to VCC + 0.5V
Operating Temperature, Topr . . . . . . . . -25°C to +85°C
Storage Temperature, Tstg . . . . . . . . . -55°C to +125°C
Power Dissipation, PT . . . . . . . . . . . . . . . . . . . . . 0.7W
Soldering Temp. & Time . . . . . . . . . . . . 260°C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (TA = 0°C to + 70°C or -25°C to 85°C, VCC = 2.7V to 3.6V, GND = 0V)
Symbol
Parameter
ILI Input Leakage Current
A62S7316-55S/70S
Min.
Max.
A62S7316-55SI/70SI
Min.
Max.
Unit
Conditions
-1
-
1 µA VIN = GND to VCC
ILO Output Leakage Current
-
ICC Active Power Supply Current
-
1
5
-
-
CE = VIH or LB = VIH or
1 µA HB = VIH or OE = VIH or
WE = VIH
VI/O = GND to VCC
5 mA CE = VIL, II/O = 0mA
ICC1
Dynamic Operating
Current
ICC2
ISB
Standby Power
ISB1 Supply Current
VOL Output Low Voltage
VOH Output High Voltage
- 50
- 10
- 0.5
- 10
- 0.4
2.2 -
-
-
-
-
-
2.2
Min. Cycle, Duty = 100%
50 mA CE = VIL, II/O = 0mA
CE = VIL, VIH = VCC,
10 mA VIL = 0V, f = 1MHz,
II/O = 0 mA
0.5 mA CE = VIH
15 µA CE ≥ VCC - 0.2V
VIN ≥ 0V
0.4 V IOL = 2.1mA
- V IOH = -1.0mA
PRELIMINARY (March, 2001, Version 0.2)
4
AMIC Technology, Inc.
5 Page 
A62S7316 Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Address
CE
HB, LB
tAS1
WE
DATA IN
DATA OUT
tWHZ4
tWC
tAW
tCW
tBW2
tWP
tDW
tWR3
tDH
tOW
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and, or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and, or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY (March, 2001, Version 0.2)
10
AMIC Technology, Inc.
11 Page | ||
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