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ACT-F512K8N-090F7C Schematic ( PDF Datasheet ) - Aeroflex Circuit Technology

Teilenummer ACT-F512K8N-090F7C
Beschreibung ACT-F512K8 High Speed 4 Megabit Monolithic FLASH
Hersteller Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology Logo 




Gesamt 21 Seiten
ACT-F512K8N-090F7C Datasheet, Funktion
ACT–F512K8 High Speed
4 Megabit Monolithic FLASH
Features
CIRCUIT TECHNOLOGY
www.aeroflex.com
s Low Power Monolithic 512K x 8 FLASH
s Industry Standard Pinouts
s TTL Compatible Inputs and CMOS Outputs s Packaging – Hermetic Ceramic
s Access Times of 60, 70, 90, 120 and 150ns
s +5V Programing, 5V ±10% Supply
s 100,000 Erase / Program Cycles
s Low Standby Current
q 32 Lead, 1.6" x .6" x .20" Dual-in-line Package (DIP),
Aeroflex code# "P4"
q 32 Lead, .82" x .41" x .11" Ceramic Flat Package
(FP), Aeroflex code# "F6"
q 32 Lead, .82" x .41" x .132" Ceramic Flat Package
(FP Lead Formed), Aeroflex code# "F7"
s Page Program Operation and Internal
Program Control Time
s Supports Full Chip Erase
s Sector Architecture
q 8 Equal size sectors of 64K bytes each
q Any Combination of Sectors ccan be erased with one
command sequence.
s Embedded Erase and Program Algorithms s Commercial, Industrial and Military
s Supports Full Chip Erase
Temperature Ranges
s
MIL-PRF-38534 Compliant Circuits Available
s
DESC SMD Pending
5962-96692 (P4,F6,F7)
Block Diagram – DIP (P4) & Flat Packages (F6,F7)
WE
OE
A0 – A18
CE
Vss
512Kx8
Vcc
8
I/O0-7
Pin Description
I/O0-7
Data I/O
A0–18 Address Inputs
WE Write Enable
CE Chip Enable
OE Output Enable
VCC Power Supply
VSS Ground
NC Not Connected
General Description
The ACT–F512K8 is a high
speed, 4 megabit CMOS
monolithic Flash module
designed for full temperature
range military, space, or high
reliability applications.
This device is input TTL and
output CMOS compatible. The
command register is written by
bringing WE to a logic low level
(VIL), while CE is low and OE is
at logic high level (VIH). Reading
is accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACT–F512K8 is
available in a choice of
eroflex Circuit Technology - Advanced Multichip Modules © SCD1668 REV A 4/28/98






ACT-F512K8N-090F7C Datasheet, Funktion
Table 3 — Commands Definitions
Command
Sequence
Bus
Write First Bus Write Second Bus Write Third Bus Write
Fourth Bus
Fifth Bus Write Sixth Bus Write
Cycle
Cycle
Cycle
Read/Write Cycle
Cycle
Cycle
Cycles
Required
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read/Reset
1 XXXH F0H
Read/Reset
4 5555H AAH 2AAAH 55H 5555H F0H
RA
RD
Autoselect
4 5555H AAH 2AAAH 55H 5555H 90H
Byte Program
6 5555H AAH 2AAAH 55H 5555H A0H
PA
PD
Chip Erase
6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Sector Erase
6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H
Sector Erase Suspend Erase can be suspended during sector erase with Address (Don’t care), Data (B0H)
Sector Erase Resume Erase can be resumed after suspend with Address (Don’t care), Data (30H)
NOTES:
1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
set-up command and data write cycles. Addresses are
latched on the falling edge of CE or WE, whichever
occurs later, while the data is latched on the rising edge
of CE or WE whichever occurs first. The rising edge of
CE or WE begins programming. Upon executing the pro-
gram algorithm command sequence the system is not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verity the programmed
cell status. The automatic programming operation is
completed when the data on D7 is equivalent to data
written to this bit at which time the device returns to the
read mode and addresses are no longer latched. The
device requires a valid address be supplied by the Sys-
tem at this time. Data Polling must be performed at the
memory location which is being programmed.
Programming is allowed in any address sequence and
across sector boundaries.
Figure 3 illustrates the programming algorithm using typ-
ical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
'unlock' write cycles. These are followed by writing the
'set-up' command. Two more 'unlock' write cycles are
then followed by the chip erase command.
Chip erase does not require the user to program the
device prior to erase. Upon executing the erase algo-
rithm (Figure 4) sequence the device automatically will
program and verify the entire memory for an all zero data
pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data in D7 is "1" (see Write Operation Status
section - Table 4) at which time the device returns to read
the mode. See Figures 4 and 9.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out of
100µs from the rising edge of the last sector erase com-
mand will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase com-
mand 30H to address in other sectors desired to be con-
currently erased. A time-out of 100µs from the rising
edge of the WE pulse for the last sector erase command
will initiate the sector erase. If another sector erase
command is written within the 100µs time-out window
the timer is reset. Any command other than sector erase
within the time-out window will reset the device to the
read mode, ignoring the previous command string.
Loading the sector erase buffer may be done in any
sequence and with any number of sectors (0 to 7).
Sector erase does not require the user to program the
device prior to erase. The device automatically pro-
grams all memory locations in the sector(s) to be erased
prior to electrical erase. When erasing a sector or sec-
tors the remaining unselected sectors are not affected.
The system is not required to provide any controls or tim-
ings during these operations.
Data Protection
The ACT–F512K8 is designed to offer protection against
accidental erasure or programming caused by spurious
system level singles that may exist during power transi-
tions. During power up the device automatically resets
the internal state machine in the read mode. Also, with
Aeroflex Circuit Technology
6 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700

6 Page









ACT-F512K8N-090F7C pdf, datenblatt
Figure 5
Toggle Bit Algorithm
Start
Read Byte
D0-D7
Address = VA
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
D6 = Toggle No
?
Yes
No
D5 = 1
?
Yes
Read Byte
D0-D7
Address = VA
D6 =
Toggle?
(Note 1)
Yes
Fail
No
Pass
Figure 6
Data Polling Algorithm
Start
Read Byte
D0-D7
Address = VA
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
D7 =
Toggle?
Yes
No
No
D5 = 1
?
Yes
Read Byte
D0-D7
Address = VA
D7 =
Data
?
No
Fail
Yes
Pass
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at
the same time as D5 changes to "1".
Note 1. D7 is rechecked even if D5 = "1" because D7 may change
simultaneously with D5.
Aeroflex Circuit Technology
12 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700

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