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ACT-F128K32N-150P3Q Schematic ( PDF Datasheet ) - Aeroflex Circuit Technology

Teilenummer ACT-F128K32N-150P3Q
Beschreibung ACT-F128K32 High Speed 4 Megabit FLASH Multichip Module
Hersteller Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology Logo 




Gesamt 20 Seiten
ACT-F128K32N-150P3Q Datasheet, Funktion
ACT–F128K32 High Speed
4 Megabit FLASH Multichip Module
Features
CIRCUIT TECHNOLOGY
www.aeroflex.com
s 4 Low Power 128K x 8 FLASH Die in One MCM
Package
s Organized as 128K x 32
q User Configurable to 256K x 16 or 512K x 8
q Upgradable to 512K x 32 in same Package Style
s Access Times of 60, 70, 90, 120 and 150ns
s +5V Programing, 5V ±10% Supply
s 100,000 Erase/Program Cycles Typical, 0°C to +70°C
s Low Standby Current
s TTL Compatible Inputs and CMOS Outputs
s Embedded Erase and Program Algorithms
s Page Program Operation and Internal Program
Control Time
s Commercial, Industrial and Military Temperature
Ranges
s MIL-PRF-38534 Compliant MCMs Available
s Industry Standard Pinouts
s Packaging – Hermetic Ceramic
q 68 Lead, .88" x .88" x .160" Single-Cavity Small
Outline gull wing, Aeroflex code# "F5" (Drops into
the 68 Lead JEDEC .99"SQ CQFJ footprint)
q 66 Pin, 1.08" x 1.08" x .160" PGA Type, No
Shoulder, Aeroflex code# "P3"
q 66 Pin, 1.08" x 1.08" x .185" PGA Type, With
Shoulder, Aeroflex code# "P7"
s Sector Architecture (Each Die)
q 8 Equal size sectors of 64K bytes each
q Any Combination of Sectors can be erased with
one command sequence
q Supports Full Chip Erase
s DESC SMD# 5962–94716 Released (P3,P7,F5)
Block Diagram – PGA Type Package(P3,P7) & CQFP(F5)
WE1 CE1 WE2 CE2 WE3 CE3 WE4 CE4
OE
A0–A16
128Kx8 128Kx8 128Kx8 128Kx8
8
I/O0-7
88
8
I/O8-15 I/O16-23 I/O24-31
Pin Description
I/O0-31 Data I/O
A0–16 Address Inputs
WE1-4 Write Enables
CE1-4 Chip Enables
OE Output Enable
VCC Power Supply
GND
Ground
NC Not Connected
General Description
The ACT–F128K32 is a high
speed, 4 megabit CMOS flash
multichip module (MCM)
designed for full temperature
range military, space, or high
reliability applications.
The MCM can be organized
as a 128K x 32 bits, 256K x 16
bits or 512K x 8 bits device and
is input TTL and output CMOS
compatible. The command
register is written by bringing
WE to a logic low level (VIL),
while CE is low and OE is at
logic high level (VIH). Reading is
accomplished by chip Enable
(CE) and Output Enable (OE)
being logically active, see
Figure 9. Access time grades of
60ns, 70ns, 90ns, 120ns and
150ns maximum are standard.
The ACT–F128K32 is
packaged in a hermetically
eroflex Circuit Technology - Advanced Multichip Modules © SCD1667 REV A 4/28/98






ACT-F128K32N-150P3Q Datasheet, Funktion
Table 3 — Commands Definitions
Command
Sequence
Bus
Write First Bus Write Second Bus Write Third Bus Write
Cycle
Cycle
Cycle
Cycle
Fourth Bus
Read/Write
Cycle
Req’d Addr Data Addr Data Addr Data Addr Data
Read/Reset
4 5555H AAH 2AAAH 55H 5555H F0H
RA
RD
Byte Program
6 5555H AAH 2AAAH 55H 5555H A0H
PA
PD
Chip Erase
6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH
Sector Erase
6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH
NOTES:
1. Address bit A15 = X = Don't Care. Write Sequences may be initiated with A15 in either state.
2. Address bit A16 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA).
3. RA = Address of the memory location to be read
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A16, A15, A14 will uniquely select any sector.
4. RD = Data read from location RA during read Operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
Fifth Bus Write Sixth Bus Write
Cycle
Cycle
Addr Data Addr Data
2AAAH 55H 5555H 10H
2AAAH 55H SA 30H
default value ensures that no spurious alteration of the
memory content occurs during the power transition.
Refer to the AC Read Characteristics and Figure 7 for the
specific timing parameters.
BYTE PROGRAMING
The device is programmed on a byte-byte basis.
Programming is a four bus cycle operation. There are
two "unlock" write cycles. These are followed by the
program set-up command and data write cycles.
Addresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE whichever occurs first. The
rising edge of CE or WE (whichever happens first) begins
programming using the Embedded Program Algorithm.
Upon executing the program algorithm command
sequence the system is not required to provide further
controls or timings. The device will automatically provide
adequate internally generated program pulses and verify
the programmed cell.
The automatic programming operation is completed
when the data on D7 (also used as Data Polling) is
equivalent to data written to this bit at which time the
device returns to the read mode and addresses are no
longer latched. Therefore, the device requires that a valid
address be supplied by the system at this particular
instance of time for Data Polling operations. Data Polling
must be performed at the memory location which is being
programmed.
Any commands written to the chip during the Embedded
Program Algorithm will be ignored.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data "0" cannot be
programmed back to a “1". Attempting to do so may
cause the device to exceed programming time limits (D5
= 1) or result in an apparent success, according to the
data polling algorithm, but a read from reset/read mode
will show that the data is still “0". Only erase operations
can convert “0"s to “1"s.
Figure 3 illustrates the programming algorithm using
typical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
'unlock' write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence (Figure 4) the
device will automatically program and verify the entire
memory for an all zero data pattem prior to electrical
erase. The erase is performed concurrently on all sectors
at the same time . The system is not required to provide
any controls or timings during these operations. Note:
Post Erase data state is all "1"s.
The automatic erase begins on the rising edge of the last
WE pulse in the command sequence and terminates
when the data on D7 is "1" (see Write Operation Status
section - Table 3) at which time the device retums to read
mode. See Figures 4 and 9.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"setup" command. Two more "unlock" write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(30H) is latched on the rising edge of WE. After a
time-out of 80µs from the rising edge of the last sector
erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the sector erase
command to addresses in other sectors desired to be
concurrently erased. The time between writes must be
less than 80µs otherwise that command will not be
accepted and erasure will start. It is recommended that
processor interrupts be disabled during this time to
guarantee this condition. The interrupts can be
re-enabled after the last Sector Erase command is
written. A time-out of 80µs from the rising edge of the
last WE will initiate the execution of the Sector Erase
command(s). If another falling edge of the WE occurs
Aeroflex Circuit Technology
6 SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700

6 Page









ACT-F128K32N-150P3Q pdf, datenblatt
Figure 5
Toggle Bit Algorithm
Start
Read Byte
D0-D7
Address = VA
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
D6 = Toggle No
?
Yes
No
D5 = 1
?
Yes
Read Byte
D0-D7
Address = VA
D6 =
Toggle?
(Note 1)
No
Yes
Fail
Pass
Figure 6
Data Polling Algorithm
Start
Read Byte
D0-D7
Address = VA
VA = Byte Address for Programming
= Any of the Sector Addresses
within the sector being erased
during sector erase operation
= XXXXH during Chip Erase
D7 = Data
?
Yes
No
No
D5 = 1
?
Yes
Read Byte
D0-D7
Address = VA
D7 =
Toggle?
(Note 1)
No
Fail
Yes
Pass
Note 1. D6 is rechecked even if D5 = "1" because D6 may stop toggling at
the same time as D5 changes to "1".
Note 1. D7 is rechecked even if D5 = "1" because D7 may change
simultaneously with D5.
Aeroflex Circuit Technology
12 SCD1667 REV A 4/28/97 Plainview NY (516) 694-6700

12 Page





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