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ACT-D1M96S Schematic ( PDF Datasheet ) - Aeroflex Circuit Technology

Teilenummer ACT-D1M96S
Beschreibung ACT-D1M96S High Speed 96 MegaBit 3.3V Synchronous DRAM Multichip Module
Hersteller Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology Logo 




Gesamt 14 Seiten
ACT-D1M96S Datasheet, Funktion
ACT-D1M96S High Speed
96 MegaBit 3.3V Synchronous DRAM
Multichip Module
Features
I 6 Low Power Micron 1M X 16 Synchronous Dynamic
Random Access Memory Chips in one MCM
I User Configureable as "2" Independent 512K X 48 X 2
Banks
I High-Speed, Low-Noise, Low-Voltage TTL (LVTTL)
Interface
I 3.3-V Power Supply (±10% Tolerance)
I Separate Logic and Output Driver Power Pins
I Two Banks for On-Chip Interleaving (Gapless
Accesses)
I Up to 50-MHz Data Rates
I CAS Latency (CL) Programmable to 2 Cycles From
Column-Address Entry
I Burst Length Programmable to 4 or 8
I Pipeline Architecture
I Cycle-by-Cycle DQ-Bus Write Mask Capability With
Upper and Lower Byte Control
I Chip Select and Clock Enable for Enhanced-System
Interfacing
I Serial Burst Sequence
I Auto-Refresh
I 4K Refresh (Total for Both Banks)
I 200-lead CQFP, cavity-up package
General Description
The ACT-D1M96S device is a high-speed 96Mbit synchronous dynamic random access memory (SDRAM)
organized as 2 independent 512K X 48 X 2 banks. All inputs and outputs of the ACT-D1M96S are compatible
with the LVTTL interface. All inputs and outputs are synchronized with the CLK input to simplify system design
and enhance use with high-speed microprocessors and caches.
BLOCK DIAGRAM
CS1
CLK1
S CKE1
E DQMU1
C DQML1
T
RAS1
CAS1
I WE1
O
A0-A11
12
N
A BANK T
BANK B
CS2
CLK2
S CKE2
E
DQMU2
DQML2
C RAS2
T CAS2
I WE2
O BA0-BA11
12
N
B BANK T
BANK B
1M X 16 or
512K X 16 X 2 Banks
16
DQ0-15
1M X 16 or
512K X 16 X 2 Banks
16
DQ48-63
1M X 16 or
512K X 16 X 2 Banks
16
DQ16-31
1M X 16 or
512K X 16 X 2 Banks
16
DQ64-79
1M X 16 or
512K X 16 X 2 Banks
16
DQ32-47
1M X 16 or
512K X 16 X 2 Banks
16
DQ80-95
eroflex Circuit Technology - Advanced Multichip Modules © SCD3369-1 REV C 5/31/00






ACT-D1M96S Datasheet, Funktion
Table 1 — Basic Command Truth Table
Command
State of
Bank(s)
CS1 RAS1 CAS1
CS2 RAS2 CAS2
WE1
WE2
A11 A10
BA11 BA10
A9-A0
BA9-BA0
Mne-
monic
Mode register set
T = deac
B = deac
L
L
L
A9,BA9 = V
L X X A8,BA8,A7,BA7 = 0 MRS
A6-A0,BA6-BA0 = V
Bank deactivate (precharge)
X
LL
H
L BS L
X DEAC
Deactivate all banks (precharge)
X
LL
H
L XH
X DCAB
Bank activate/row-address entry SB = deac L
L
H
H BS V
V ACTV
Column-address entry/write
operation
SB = actv L
H
L
L BS L
V WRT
Column-address entry/write
operation with auto-deactivate
SB = actv L
H
L
L BS H
V WRT-P
Column-address entry/read
operation
SB = actv L
H
L
H BS L
V READ
Column-address entry/read
operation with auto-deactivate
SB = actv L
H
L
H BS H
V READ-P
Burst stop
SB = actv L
H
H
L XX
X STOP
No operation
X
LH
H
H XX
X NOOP
Control-input inhibit/no operation
X
HX
X
X XX
X DESL
Auto refresh§
T = deac
B = deac
L
L
L
H XX
X REFR
NOTES:
† For execution of these commands on cycle n:
-CKE (n-1) must be high, or
-tCES and nCLE must be satisfied for clock-suspend exit.
DQMx(n) is a don’t care.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
§ Auto-refresh entry requires that all banks be deactivated or in an idle state prior to the command entry.
Legend:
n = CLK cycle number, L = Logic low, H = Logic high, X = Don’t care, either logic low or logic high, V = Valid, T = Bank T, B = Bank B, actv = Activated, deac = Deactivated, BS
= Logic high to select bank T; logic low to select bank B, SB = Bank selected by A11 at cycle n
Table 2 — Clock Enable (CKE) Command Truth Table
Command
State of Bank(s)
CKE CKE
(n-1) (n)
CS
(n)
RAS
(n)
CAS
(n)
WE
(n)
CLK suspend on cycle (n + 1)
T = access operation
B = access operation
H
L
X
X XX
CLK suspend exit on cycle (n + 1)
T = access operation
B = access operation
L
H
X
X XX
NOTES:
† For execution of these commands, A0-A11 (n) and DQMx (n) are don’t cares.
‡ All other unlisted commands are considered vendor-reserved commands or illegal commands.
¶ A bank is no longer in an access operation one cycle after the last data-out cycle of a read operation, and two cycles after the last data-in cycle
of a write operation. Neither the PDE nor the HOLD command is allowed on the cycle immediately following the last data-in cycle of a write operation.
Legend:
n = CLK cycle number, L = Logic low, H = Logic high, X = Don’t care, either logic low or logic high, T = Bank T, B = Bank B
Mnemonic
HOLD
Aeroflex Circuit Technology
6 SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700

6 Page









ACT-D1M96S pdf, datenblatt
Package Information – "F20" – CQFP 200 Leads
150
151
1.230 (31.242)
1.220 (30.988)
49 Spaces at .025
(49 Spaces at .635)
Pin 1 Chamfer
200
1
Detail "A"
1.464 (37.186) SQ
1.436 (36.474) SQ
.1.290 (32.766) SQ
REF
101
100
.010R MIN
.010R MIN
.015 (.381)
.009 (.229)
0°±5°
.130 (3.302)
MAX
.100 (2.540)
.080 (2.032)
51
50
.035 (.889)
.025 (.635)
.012 (.304)
.009 (.229)
Detail "A"
.045 (1.143)
REF
.115 (2.921)
MAX
1.664 (42.266)
1.596 (40.538)
.066 (1.676)
.054 (1.372)
Note: 1. All Dimensions in inches (Millimeters) MAX or Typical where noted.
MIN
A0-A10
BA0-BA10
A11,BA11
CAS1,CAS2
CKE1,CKE2
CLK1,CLK2
CS1,CS2
DQ0-DQ95
Pin Nomenclature
Address Inputs
A0-A10, BA0-BA10 Row Addresses
A0-A7, BA0-BA7 Column Addresses
A10, BA10 Automatic-Precharge Select
Bank Select
Column-Address Strobe
Clock Enable
System Clock
Chip Select
SDRAM Data Input/Output
DQML1,2
DQMU1,2
RAS1,RAS2
VCC
VCCQ
VSS
VSSQ
WE1,WE2
Data/Input Mask Enables
Row-Address Strobe
Power Supply
Power Supply for Output Drivers
Ground
Ground for Output Drivers
Write Enable
Aeroflex Circuit Technology
12 SCD3369-1 REV C 5/31/00 Plainview NY (516) 694-6700

12 Page





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