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ACT-7000SC-250F17T Schematic ( PDF Datasheet ) - Aeroflex Circuit Technology

Teilenummer ACT-7000SC-250F17T
Beschreibung ACT 7000SC 64-Bit Superscaler Microprocessor
Hersteller Aeroflex Circuit Technology
Logo Aeroflex Circuit Technology Logo 




Gesamt 25 Seiten
ACT-7000SC-250F17T Datasheet, Funktion
ACT 7000SC
64-Bit Superscaler Microprocessor
Features
Full militarized QED RM7000 microprocessor
Dual Issue symmetric superscalar microprocessor with
instruction prefetch optimized for system level
price/performance
150, 200, 210, 225 MHz operating frequency
Consult Factory for latest speeds
MIPS IV Superset Instruction Set Architecture
High performance interface (RM52xx compatible)
600 MB per second peak throughput
75 MHz max. freq., multiplexed address/data
Supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)
IEEE 1149.1 JTAG (TAP) boundary scan
Integrated primary and secondary caches - all are 4-way set
associative with 32 byte line size
16KB instruction
16KB data: non-blocking and write-back or write-through
256KB on-chip secondary: unified, non-blocking, block writeback
MIPS IV instruction set
Data PREFETCH instruction allows the processor to overlap cache
miss latency and instruction execution
Floating point combined multiply-add instruction increases
performance in signal processing and graphics applications
Conditional moves reduce branch frequency
Index address modes (register + register)
Embedded supply de-coupling capacitors and additional PLL
filter components
Integrated memory management unit (ACT52xx compatible)
Fully associative joint TLB (shared by I and D translations)
48 dual entries map 96 pages
4 entry DTLB and 4 entry ITLB
Variable page size (4KB to 16MB in 4x increments)
Embedded application enhancements
Specialized DSP integer Multiply-Accumulate instruction,
(MAD/MADU) and three-operand multiply instruction (MUL/U)
Per line cache locking in primaries and secondary
Bypass secondary cache option
I&D Test/Break-point (Watch) registers for emulation & debug
Performance counter for system and software tuning & debug
Ten fully prioritized vectored interrupts - 6 external, 2 internal, 2
software
Fast Hit-Writeback-Invalidate and Hit-Invalidate cache operations
for efficient cache management
High-performance floating point unit - 600 M FLOPS
maximum
Single cycle repeat rate for common single-precision operations
and some double-precision operations
Single cycle repeat rate for single-precision combined multiply-
add operations
Two cycle repeat rate for double-precision multiply and
double-precision combined multiply-add operations
Fully static CMOS design with dynamic power down logic
Standby reduced power mode with WAIT instruction
4 watts typical @ 2.5V Int., 3.3V I/O, 200MHz
208-lead CQFP, cavity-up package (F17)
208-lead CQFP, inverted footprint (F24), with the same pin
rotation as the commercial QED RM5261
BLOCK DIAGRAM
On - Chip 256K Byte Secondary Cache, 4 - Way Set Associative
Secondary Tags
Set A
Secondary Tags
Set B
Secondary Tags
Set C
Secondary Tags
Set D
Primary Data Cache
4 - Way Set Associative
DTag
DTLB
ITag
ITLB
Primary Instruction Cache
4 - Way Set Associative
A/D Bus
Pad Bus
Store Buffer
Write Buffer
Read Buffer
D Bus
Pad Buffer
Address Buffer
F-Pipe Bus
Prefetch Buffer
Instruction Dispatch Unit
F Pipe Register
M Pipe Register
M-Pipe Bus
Floating-Point
Load / Align
Floating-Point
Register File
Packer / Unpacker
Comparator
Floating-Point
MultAdd, Add, Sub,
Cvt, Div, Sqrt
Multiplier Array
Joint TLB
Coprocessor 0
DVA
System / Memory
Control
IVA
PC Incrementer
Branch PC Adder
ITLB Virtuals
Program Counter
Load Aligner
Integer Register File
M Pipe
F Pipe
Adder
Adder
StAin/Sh
Logicals
Shifter
Logicals
FA Bus
DTLB Virtuals
PLL/Clocks
Int Mult. Div. Madd
eroflex Circuit Technology – MIPS RISC Microprocessors © SCD7000SC REV B 7/30/01






ACT-7000SC-250F17T Datasheet, Funktion
address translation buffer, or DTLB, a Joint TLB, or
JTLB, and coprocessor registers used by the virtual
memory mapping sub-system.
System Control Coprocessor Registers
The ACT 7000SC incorporates all system control
coprocessor (CP0) registers internally. These
registers provide the path through which the virtual
memory system’s page mapping is examined and
modified, exceptions are handled, and operating
modes are controlled (kernel vs. user mode,
interrupts enabled or disabled, cache features). In
addition, the ACT 7000SC includes registers to
implement a real-time cycle counting facility, to aid in
cache and system diagnostics, and to assist in data
error detection.
To support the non-blocking caches and enhanced
interrupt handling capabilities of the ACT 7000SC,
both the data and control register spaces of CP0 are
supported by the ACT 7000SC. In the data register
space, that is the space accessed using the MFC0
and MTC0 instructions, the ACT 7000SC supports the
same registers as found in the RM5200, R4000 and
R5000 families. In the control space, that is the space
accessed by the previously unused CTC0 and CFC0
instructions, the ACT 7000SC supports five new
registers. The first three of these new 32-bit registers
support the enhanced interrupt handling capabilities
and are the Interrupt Control, Interrupt Priority Level
Lo (IPLLO), and Interrupt Priority Level Hi (IPLHI)
registers. These registers are described further in the
section on interrupt handling. The other two registers,
Imprecise Error 1 and Imprecise Error 2, have been
added to help diagnose bus errors which occur on
non-blocking memory references.
Figure 4 shows the CP0 registers.
Virtual to Physical Address Mapping
The ACT 7000SC provides three modes of virtual
addressing:
• user mode
• supervisor mode
• kernel mode
This mechanism is available to system software to
provide a secure environment for user processes. Bits
in the CP0 Status register determine which virtual
addressing mode is used. In the user mode, the ACT
7000SC provides a single, uniform virtual address
space of 256GB (2GB in 32-bit mode).
When operating in the kernel mode, four distinct
virtual address spaces, totalling 1024GB (4GB in
32-bit mode), are simultaneously available and are
differentiated by the high-order bits of the virtual
address.
The ACT 7000SC processor also supports a
supervisor mode in which the virtual address space is
256.5GB (2.5GB in 32-bit mode), divided into three
regions based on the high-order bits of the virtual
address. Figure 5 shows the address space layout for
32-bit operation.
PageMask
5*
EntryHi
10*
EntryLo0
2*
EntryLo1
3*
47
TLB
(entries protected
from TLBWR)
0
LLAddr
17*
TagLo
28*
TagHi
29*
Info
7*
Index
0*
Random
1*
Wired
6*
PRid
15*
Config
16*
Context
4*
Count
9*
Status
12*
EPC
14*
Watch2
19*
ECC
26*
BadVAddr Perf Counter
8* 25*
Compare Perf Ctr Cntrl
11* 22*
Cause
13*
Watch1
18*
Watch Mask
24*
IPLLO
18*
IPLHI
19*
IntControl
20*
Imp Error 1
26*
Xcontext
20*
Imp Error 2
27*
CacheErr
27*
ErrorEPC
30*
Used for memory
management
Aeroflex Circuit Technology
* Registered number
Used for exception
processing
Figure 4 – CP0 Registers
Control Space Registers
6 SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

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ACT-7000SC-250F17T pdf, datenblatt
transaction. The ACT 7000SC samples these signals
before deasserting the address on read and write
requests.
ExtRqst* and Release* are used to transfer control
of the SysAD and SysCmd buses from the processor
to an external device. When an external device needs
to control the interface, it asserts ExtRqst*. The ACT
7000SC responds by asserting Release* to release
the system interface to slave state.
ValidOut* and ValidIn* are used by the ACT
7000SC and the external device respectively to
indicate that there is a valid command or data on the
SysAD and SysCmd buses. The ACT 7000SC
asserts ValidOut* when it is driving these buses with
a valid command or data, and the external device
drives ValidIn* when it has control of the buses and is
driving a valid command or data.
System Interface Operation
The ACT 7000SC can issue read and write
requests to an external device, while an external
device can issue null and write requests to the ACT
7000SC.
For processor reads, the ACT 7000SC asserts
ValidOut* and simultaneously drives the address and
read command on the SysAD and SysCmd buses. If
the system interface has RdRdy* asserted, then the
processor tristates its drivers and releases the system
interface to slave state by asserting Release*. The
external device can then begin sending data to the
ACT 7000SC.
Figure 7 shows a processor block read request and
the external agent read response for a system with a
transaction.
The read latency is 4 cycles (ValidOut* to
ValidIn*), and the response data pattern is DDxxDD.
Figure 9 shows a processor block write where the
processor was programmed with write-back data rate
boot code 2, or DDxxD-Dxx.
Data Prefetch
The ACT 7000SC is the first Aeroflex design to
support the MIPS IV integer data prefetch (PREF) and
floating-point data prefetch (PREFX) instructions.
These instructions are used by the compiler or by an
assembly language programmer when it is known or
suspected that an upcoming data reference is going
to miss in the cache. By appropriately placing a
prefetch instruction, the memory latency can be
hidden under the execution of other instructions. If the
execution of a prefetch instruction would cause a
memory management or address error exception the
prefetch is treated as a NOP.
The “Hint” field of the data prefetch instruction is
used to specify the action taken by the instruction.
The instruction can operate normally (that is, fetching
data as if for a load operation) or it can allocate and fill
a cache line with zeroes on a primary data cache
miss.
Enhanced Write Modes
The ACT 7000SC implements two enhancements
to the original R4000 write mechanism: Write Reissue
and Pipeline Writes. In write reissue mode, a write
rate of one write every two bus cycles can be
achieved. A write issues if WrRdy* is asserted two
cycles earlier and is still asserted during the issue
cycle. If it is not still asserted then the last write will
reissue. Pipe-lined writes have the same two bus
cycle write repeat rate, but can issue one additional
write following the deassertion of WrRdy*.
External Requests
The ACT 7000SC can respond to certain requests
issued by an external device. These requests take
one of two forms: Write requests and Null requests.
An external device executes a write request when it
wishes to update one of the processors writable
resources such as the internal interrupt register. A null
request is executed when the external device wishes
the processor to reassert ownership of the processor
external interface. Typically a null request will be
executed after an external device, that has acquired
control of the processor interface via ExtRqst*, has
SysClock
SysAD
SysCmd
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Aeroflex Circuit Technology
Addr
Read
Data0 Data1
nData nData
Data2 Data3
nData NEOD
Figure 7 – Processor Block Read
12 SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700

12 Page





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