PDF AD2S93 Data sheet ( Hoja de datos )

Número de pieza	AD2S93
Descripción	Low Cost LVDT-to-Digital Converter
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES Full Function Monolithic LVDT-to-Digital Converter Absolute Serial Data Output Uncommitted Differential Input Repeatability Remote Diagnostics 14-Bit Resolution Industrial Temperature Range 28-Pin PLCC Low Power APPLICATIONS Industrial Gauging Industrial Process Control Linear Positioning Systems Linear Actuator Control Automotive Motion Sensing and Control Torque Sensing Conditioner AC Strain Gages Conditioning Avionics Low Cost LVDT-to-Digital Converter AD2S93 FUNCTIONAL BLOCK DIAGRAM REFERENCE (PRIMARY EXCITATION) REF DIFFERENTIAL (SECONDARY A VOLTAGE) B R4 GAIN DIFF R3 LOS VDD OVR UNR NULL CS ACERROR C3 C4 R5 R6 DEMODIN ERROR AMP AC RATIO BRIDGE PHASE SENSITIVE DEMODULATOR DEMOD OUT R1 R7 INTIN LOS DECODE LOGIC UP-DOWN COUNTER LATCHES FREQUENCY SHAPING VCO C1 R2 C2 VEL VCO GAIN DIR CLKOUT DATA SCLK SERIAL INTERFACE AD2S93 GENERAL DESCRIPTION The AD2S93 is a complete 14-bit resolution tracking LVDT-to- digital converter. A Type II tracking loop is employed to track the A–B input and produce a digital output equal to (A–B)/ (REF/2), where REF is a fixed amplitude ac reference phase co- herent with the A–B input. This allows the measurement of any 2-, 3-, 4- and 5-wire LVDT or linear amplitude modulated in- put. The operating frequency range is from 360 Hz to 10 kHz with user definable bandwidth set externally within a range of 45 Hz to 1250 Hz. The AD2S93 has a 16-bit serial output. The MSB (LOS), read first, indicates a loss of the signal A, B, or reference inputs to the converter or transducer. The second and third MSBs are flags indicating whether [–REF/2 (UNR) ≤ A–B ≤ +REF/2 (OVR]) is outside the linear operating range of the converter. The dis- placement data is presented as 13-bit offset binary giving a ± 12- bit operating range. LOS, OVR and UNR are pinned out on the device, in addition a NULL flag is available which is set when (A–B) = 0. Absolute displacement information is accessed when CS is taken LO followed by the application of an external clock (SCLK) with a maximum rate of 2 MHz. Data is read MSB first. When CS is high the DATA output is high impedance; this allows daisy chaining of more than one converter onto a common bus. The A, B differential input allows the user to scale the A, B in- puts between 1 and 10. This enables the user to accurately set up the inputs matching the REF input to the DIFF output. The DIFF output is the resultant A–B. The AD2S93 operates using ± 5 V ± 5% power supplies and is fabricated on Analog Devices’ linear compatible CMOS process (LC2MOS). The (LC2MOS) is a mixed technology process that combines precision bipolar circuits with low power logic. PRODUCT HIGHLIGHTS Complete LVDT-to-Digital Interface. The AD2S93 pro- vides the complete solution for digitizing LVDT signals to 14- bit resolution. Serial 16-Bit Output Data. One 16-bit read from the AD2S93 determines input signal continuity (LOS), over and underrange detection and 13 bits of offset binary displacement information. High Accuracy Grade in Low Cost Package. 0.05% and 0.1% integral linearity over the full –40°C to +85°C operating temperature range. Uncommitted Differential Input. Allows configuration of 2-, 3-, 4- and 5-wire LVDTs. Multiple Converter Interfacing. High impedance data out- put and a simple three-wire interface reduces cabling and elimi- nates bus contention. Low Power. 70 mW power consumption (typ). REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 1 page GLOSSARY OF TERMS INTEGRAL LINEARITY Integral linearity deviation as a percent of full scale. A 0.1% de- viation is equivalent to 8-LSB change on the output. Gain The converter gain is the maximum variation in the ratio of A–B/REF/2 to the maximum digital input. Output Offset The output offset is the digital output code when the analog in- put signal A–B = 0. Overrange (OVR) OVR goes high when A–B is in phase with REF and larger than REF/2. Underrange (UNR) UNR goes high when A–B is out of phase with REF and larger than REF/2. PRINCIPLE OF OPERATION The AD2S93 is based on a Type 2 tracking closed-loop prin- ciple. The output tracks the position of the LVDT without the need for external convert and wait states. As the transducer moves through a position equivalent to the least significant bit weighting, the output is updated by one LSB. On the AD2S93, CLKOUT updates corresponding to one LSB increment. Fig- ure 1 illustrates the principle of operation. REFERENCE (PRIMARY EXCITATION) REF DIFFERENTIAL (SECONDARY A VOLTAGE) B R4 GAIN DIFF R3 LOS VDD OVR UNR NULL CS ACERROR C3 C4 R5 R6 DEMODIN ERROR AMP AC RATIO BRIDGE PHASE SENSITIVE DEMODULATOR DEMOD OUT R1 R7 INTIN LOS DECODE LOGIC UP-DOWN COUNTER LATCHES FREQUENCY SHAPING VCO C1 R2 C2 VEL VCO GAIN DIR CLKOUT DATA SCLK SERIAL INTERFACE AD2S93 AD2S93 Because the conversion depends on the ratio of the input signals (ratiometric ac bridge), the AD2S93 is remarkably tolerant of input amplitude and frequency. This, combined with the defin- able Type 2 tracking closed-loop guarantees the AD2S93's re- peatability for a given input. A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null the output of the ACERROR. When this is accomplished the word state of the up/down counter equals within the rated accuracy of the converter, the LVDT position output. For more information on the operation of the converter, see “Circuit Dynamics” section. DATA FORMAT OPERATING RANGE The AD2S93 operating range is defined in Figure 2. The lin- earity and specified operating range of the converter is the cen- tral two 12-bit quadrants through zero. The corresponding input relationship is –REF/2 ≤ A–B ≤ +REF/2, (± is used to de- note phase coherency). The sign bit is low for inputs with A–B in phase with REF. The two remaining 12-bit quadrants are used to denote over (OVR) and underrange (UNR). OVR goes high when A–B is in phase with REF and larger than REF/2. UNR goes high when A–B is out of phase with REF and larger than REF/2. LOS is an open drain output which pulls high when A and/or B are removed or REF is removed (see “Inbuilt Diagnostics”), or A + B is less than 100 mV. SCALING THE INPUTS In order to match the LVDT output to the AD2S93 output, the inputs to the AD2S93 need to be scaled. The operating range is illustrated in Figure 2. The AD2S93 operates across ± 12-bit range where the remaining 12-bit quadrants are used to denote overrange and underrange. The output position word is a func- tion of the ratio between A–B and VREF (see Figure 2) where: ±FSR = ( A − B ) VREF /2 Figure 1. Functional Block Diagram REV. A –5– 5 Page The small step response is given in Figure 12, and is the time taken for the converter to settled to within 1 LSB. ts = 7 ms (14-bit resolution) The large step response (steps >5% of FSR) applies when the error voltage will exceed the linear range of the converter. Typi- cally it will take three times longer to reach the first peak FSR. In response to a velocity step [VELOUT/(dθ/dt)] the velocity output will exhibit the same response characteristics as outlined above. 2%FS 0 0 4 8 12 16 Figure 12. Small Step Response 20 AD2S93 SOURCES OF ERROR ACCELERATION ERROR A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant Ka of the converter. Ka = input acceleration position The numerator and denominator’s units must be consistent. Ka does not define maximum input acceleration, only the error due to its acceleration. The maximum acceleration allowable before the converter loses track is dependent on the positional accuracy requirement of the system. Position Error × Ka = LSB/sec2 Ka can be used to predict the output position error for a given input acceleration. The AD2S93 in the example has a Ka = 13.44 × 106 sec-2 if we apply an input accelerating at 100 × 214 LSB/sec2. [ ]input acceleration LSB/sec2 Error in LSBs = [ ]Ka sec-2 = 100 × 214 = 0.12 LSBs 13.44 × 106 REV. A –11– 11 Page

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