PDF AD2S1200 Data sheet ( Hoja de datos )

Número de pieza	AD2S1200
Descripción	12-Bit R/D Converter with Reference Oscillator
Fabricantes	Analog Devices
Logotipo
Hay una vista previa y un enlace de descarga de AD2S1200 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas
No Preview Available ! 12-Bit R/D Converter with Reference Oscillator AD2S1200 FEATURES Complete monolithic R/D converter Parallel and serial 12-bit data ports System fault detection Absolute position and velocity outputs Differential inputs ±11 arc minutes of accuracy 1,000 rps maximum tracking rate, 12-bit resolution Incremental encoder emulation (1,024 pulses/rev) Programmable sinusoidal oscillator on-board Compatible with DSP and SPI® interface standards 204.8 kHz square wave output Single-supply operation (5.00 V ± 5%) −40°C to +125°C temperature rating 44-lead LQFP package 4 kV ESD protection GENERAL DESCRIPTION The AD2S1200 is a complete 12-bit resolution tracking resolver- to-digital converter, integrating an on-board programmable sinusoidal oscillator that provides sine wave excitation for resolvers. An external 8.192 MHz crystal is required to provide a precision time reference. This clock is internally divided to generate a 4.096 MHz clock to drive all the peripherals. The converter accepts 3.6 V p-p ± 10% input signals, in the range of 10 kHz to 20 kHz on the Sin and Cos inputs. A Type II servo loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The bandwidth of the converter is set internally to 1.7 kHz with an external 8.192 MHz crystal. The maximum tracking rate is 1,000 rps. FUNCTIONAL BLOCK DIAGRAM REFBYP REFOUT FS1 FS2 CLKIN XTALOUT (8.192MHz) EXC EXC SinLO Sin CosLO Cos A B NM SAMPLE AD2S1200 VOLTAGE REFERENCE (4.096MHz) INTERNAL CLOCK GENERATOR REFERENCE OSCILLATOR (DAC) (204.8kHz) CLOCK DIVIDER SYNTHETIC REFERENCE FAULT INDICATORS ADC ANGLE θ ADC ERROR MONITOR MONITOR CALCULATION/ SIGNAL ERROR DEMODULATOR ERROR MONITOR ANGLE φ DIGITAL FILTER ENCODER EMULATION POSITION INTEGRATOR VELOCITY INTEGRATOR CPO DOS LOT DIR POSITION REGISTER VELOCITY REGISTER MULTIPLEXER DATA BUS OUTPUT CS RD RESET RDVEL SOE DB11 SO DB10 SCLK Figure 1. DB9–DB0 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. 1 page AD2S1200 Parameter FAULT DETECTION BLOCK (CONT.) DOS Sin/Cos Threshold Sin/Cos Mismatch Min 4.0 Angular Accuracy (Worst Case) Angular Latency (Worst Case) Time Latency LOT Tracking Threshold Time Latency Hysteresis VOLTAGE REFERENCE REFOUT Drift PSRR CHARGE PUMP OUTPUT (CPO) Frequency Duty Cycle POWER SUPPLY IDD Dynamic ELECTRICAL CHARACTERISTICS VIL Voltage Input Low VIH Voltage Input High VOL Voltage Output Low VOH Voltage Output High IIL Low Level Input Current IIH High Level Input Current IOZH High Level Three-State Leakage IOZL Low Level Three-State Leakage 4 2.39 2.0 4.0 −10 −10 Typ Max 4.09 4.2 385 420 30 60 125 5 1.1 2.47 2.52 70 −60 204.8 50 18 0.8 0.4 10 10 Unit Conditions/Comments V p-p mV Degrees Degrees µs DOS goes low when Sin or Cos exceeds threshold. DOS latched low when Sin/Cos amplitude mismatch exceeds the threshold. DOS indicated before angular output error exceeds limit. Maximum electrical rotation before DOS is indicated. Degrees ms Degrees LOT goes low when internal error signal exceeds threshold. Guaranteed by design. Guaranteed by design V ppm/°C dB ±IOUT = 100 µA kHz Square wave output % mA V V V 2 mA load V −1 mA load µA µA µA µA Rev. 0 \| Page 5 of 24 5 Page CONNECTING THE CONVERTER Refer to Figure 5. Ground should be connected to the AGND pin and DGND pin. Positive power supply VDD = +5 V dc ± 5% should be connected to the AVDD pin and DVDD pin. Typical values for the decoupling capacitors are 10 nF and 4.7 µF, respectively. These capacitors should be placed as close to the device pins as possible, and should be connected to both AVDD and DVDD. If desired, the reference oscillator frequency can be changed from the nominal value of 10 kHz using FS1 and FS2. Typical values for the oscillator decoupling capacitors are 20 pF. Typical values for the reference decoupling capacitors are 10 µF and 0.01 µF, respectively. S2 R2 10nF 10µF R1 S6 S3 S1 4.7µF 5V BUFFER CIRCUIT BUFFER CIRCUIT 10nF 44 43 42 41 40 39 38 37 36 35 34 5V 1 DVDD 2 3 4 5 6 7 8 9 10 11 AD2S1200 33 RESET 32 31 30 29 28 27 26 25 24 DGND 23 12 13 14 15 16 17 18 19 20 21 22 5V 8.912 MHz 4.7µF 10nF 20pF 20pF Figure 5. Connecting the AD2S1200 to a Resolver AD2S1200 The gain of the buffer depends on the type of resolver used. Since the specified excitation output amplitudes are matched to the specified Sin/Cos input amplitudes, the gain of the buffer is determined by the attenuation of the resolver. In this recommended configuration, the converter introduces a VREF/2 offset in the Sin, Cos signals coming from the resolver. Of course, the SinLO and CosLO signals may be connected to a different potential relative to ground, as long as the Sin and Cos signals respect the recommended specifications. Note that since the EXC/EXC outputs are differential, there is an inherent gain of 2×. For example, if the primary to secondary turns ratio is 2:1, the buffer will have unity gain. Likewise, if the turns ratio is 5:1, the gain of the buffer should be 2.5×. Figure 6 suggests a buffer circuit. The gain of the circuit is Gain = −(R2 / R1) and VOUT = VREF × 1+ R2 R1    −  R2 R1 ×VIN  VREF is set so that VOUT is always a positive value, eliminating the need for a negative supply. EXC/EXC (VIN) R2 R1 (VREF) 12V 442Ω 1.24kΩ 5V 12V 2.7kΩ 12V 33Ω VOUT 33Ω 2.7kΩ Figure 6. Buffer Circuit Separate screened twisted cable pairs are recommended for analog inputs Sin/SinLO and Cos/CosLO. The screens should terminate to REFOUT. To achieve the dynamic performance specified, an 8.192 MHz crystal must be used. Rev. 0 \| Page 11 of 24 11 Page

Páginas	Total 24 Páginas
PDF Descargar	[ Datasheet AD2S1200.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AD2S1200	12-Bit R/D Converter with Reference Oscillator	Analog Devices
AD2S1205	12-Bit RDC	Analog Devices

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar