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AD1991 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer AD1991
Beschreibung Class D/1-Bit Audio Power Output Stage
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 11 Seiten
AD1991 Datasheet, Funktion
Class D/1-Bit Audio Power Output Stage
AD1991
FEATURES
Class D/1-Bit Audio Power Output Stage
5 V Analog and Digital Supply Voltages
Power Stage Power Supply 8 V to 20 V
Output Power @ 0.1% THD + N
Stereo Mode
2 ؋ 20 W @ 4 @ 14.4 V
2 ؋ 20 W @ 8 @ 20 V
Mono Mode
1 ؋ 40 W @ 4 @ 20 V
RON < 320 m(per Transistor)
Efficiency > 85% @ Full Power/8
Clickless Mute Function
Turn-On and Turn-Off Pop Suppression
Short-Circuit Protection
Overtemperature Protection
Data Loss Protection
2-Channel BTL Outputs or
4-Channel Single-Ended Outputs
52-Lead Exposed Pad TQFP Package
Low Cost DMOS Process
APPLICATIONS
PC Audio Systems
Minicomponents
Automotive Amplifiers
Home Theater Systems
Televisions
GENERAL DESCRIPTION
The AD1991 is a 2-channel BTL or 4-channel single-ended
class D audio power output stage. The part is configured during
reset to be in either 2-channel mode or 4-channel mode.
To protect the IC as well as the connected speakers, the AD1991
provides turn-on and turn-off pop suppression, short-circuit
protection, and overtemperature shutdown. To control the IC,
a power-down/reset input and a mute pin are available.
The output stage can be operated over a power supply range
from 8 V to 20 V.
In 2-channel mode, Transistors A1, B2, C1, and D2 are turned
on by a Logic 1 on inputs INA and INC, and Transistors A2,
B1, C2, and D1 are turned on by a Logic 0 on inputs INA and
INC. In 4-channel mode, Transistors A1, B1, C1, and D1 are
turned on by a Logic 1 on the four inputs, and Transistors A2,
B2, C2, and D2 are turned on by a Logic 0 on the four inputs
(see the Functional Block Diagrams).
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FUNCTIONAL BLOCK DIAGRAMS
2-Channel Mode
AVDD DVDD
INA
LEFT
INPUT
PVDD
6
OUTA
A1
3
A2
INB
INC
RIGHT
INPUT
B1
B2
LEVEL SHIFTER
AND
SWITCH CONTROL
H-BRIDGE
C1
C2
OUTB
3
OUTC
3
IND
CLK
RST/PDN
MUTE
D1
D2
،n
THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL
OUTD
3
CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS
4 2 14
AGND DGND TEST PGND
CONTROL
4-Channel Mode
AVDD DVDD
PVDD
6
INA A1 OUTA
3
A2
INB B1 OUTB
3
B2
LEVEL SHIFTER
AND
SWITCH CONTROL
H-BRIDGE
INC C1 OUTC
3
C2
LOAD
REQUIRING
DC VOLTAGE
SUPPLY
IND
CLK
RST/PDN
MUTE
D1
D2
،n
THERMAL PROTECTION
SHORT-CIRCUIT PROTECTION
MUTE CONTROL
OUTD
3
LOAD
REQUIRING
DC VOLTAGE
SUPPLY
CURRENT OVERLOAD
THERMAL SHUTDOWN
THERMAL WARNING
DATA LOSS
4 2 14
AGND DGND TEST PGND
CONTROL
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






AD1991 Datasheet, Funktion
AD1991
FUNCTIONAL DESCRIPTION
Device Architecture
The AD1991 is an 8-transistor, audio, power output stage. The
AD1991 is arranged internally as four transistor pairs that can
be used as two H-bridge outputs (2-channel mode) or as four
single-ended outputs (4-channel mode), using either two or four
TTL compatible inputs to control the transistors. A dead time
is automatically provided between the switching of the high-
side transistor and low-side transistor when the control inputs
change level, to ensure that both the high-side transistor and
low-side transistor are never on at the same time.
Clock Source and Channel Mode Selection
When the AD1991 is brought out of reset, the logic levels on
MODE0 and MODE1 are latched internally. MODE0 determines
the internal state machine clock source. MODE1 determines the
channel mode and the function of ERR0 (see Tables I and II.)
When the internal clock is used, the CLK pin should not be
connected.
Table I. Clock Source Selection
MODE0
0
1
CLK Source
Internal
External
Table II. Channel Mode Selection
MODE1 Channel Mode
ERR0 Function
0 2-Channel Mode Data Loss Detection Output
1 4-Channel Mode Low-Side Disable Input
2-Channel Mode
Two loads are connected differentially—across OUTA and OUTB
and across OUTC and OUTD. Inputs INB and IND are unused
and should be tied to an appropriate dc voltage (see the Edge
Speed and Nonoverlap Settings section). In this mode, ERR0 is
an error output used to indicate data loss, which occurs when
there are no transitions on INA or INC for more than 50 ms.
This signal condition is hazardous in 2-channel mode because it
can cause a potentially large and harmful dc voltage across the
differential loads. Table III shows the input/output relationship.
Table III. Input/Output Relationship in 2-Channel Mode
Input
INA
INC
Controlled Output
OUTA, OUTB
OUTC, OUTD
4-Channel Mode
The 4-channel mode has two types of configuration: audio and
power supply. Neither of these configurations require data loss
detection. In the audio configuration, each single-ended load is
connected to the output through a blocking capacitor, which
prevents dc from reaching the load, thereby negating the need
for data loss detection. While in the power supply configuration,
it is desired to maintain a dc voltage on the load, also negating
the need for data loss detection. When used in the power supply
configuration, the four low-side transistors can also be disabled
and left permanently open if desired. This allows the loads to be
driven by switching only the high-side transistor on and off.
ERR0 is an input in 4-channel mode and is used to select
whether the four low-side transistors are enabled or disabled,
with 0 selecting disabled and 1 selecting enabled. Table IV
summarizes the function of ERR0 in this mode. Table V shows
the input/output relationship.
Table IV. ERR0 Function in 4-Channel Mode
ERR0 Low-Side Transistor Status
0 Disabled
1 Enabled
Table V. Input/Output Relationship in 4-Channel Mode
Input
INA
INB
INC
IND
Controlled Output
OUTA
OUTB
OUTC
OUTD
1-Channel Mode
One load is connected differentially—across OUTA and OUTC,
and OUTB and OUTD. This mono operation is established
by configuring the part for 2-channel mode and externally
connecting INA to INC, OUTA to OUTC, and OUTB to
OUTD (see Figure 4).
Thermal Protection
The AD1991 features thermal protection. When the die tempera-
ture exceeds approximately 135°C, the thermal warning error
output (ERR2) is asserted. If the die temperature exceeds
approximately 150°C, the thermal shutdown error output (ERR3)
is asserted. If this occurs, the part shuts down to prevent damage
to the part. When the die temperature drops below approximately
120°C, both error outputs de-assert and the part returns to nor-
mal operation.
Overcurrent Protection
The AD1991 features overcurrent or short-circuit protection. If
the current through any power transistors exceeds 5 A, the part
is muted and the overcurrent error output (ERR1) is asserted.
This is a latched error and does not clear automatically. To clear
the error condition and restore normal operation, the part must
be reset or MUTE must be asserted and de-asserted.
–6– REV. 0

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